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Old 5th Dec 2021, 6:56 pm   #1
dominicbeesley
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Default A new Verilog core SC/MP - checking against real timings

Hello,

After a break of 18 months or so I decided to pick up where I'd left off with my attempts at a System Verilog SC/MP core. I decided to get it at least running before trying to continue with the experiments I was doing with a real sc/mp to test the timings and bus behaviours.

I've put the results so far up on GitHub at https://github.com/dominicbeesley/scmp

I've not rigorously checked but all the instructions should be timing accurate in terms of the number of cycles each takes to execute, but not necessarily perfect in terms of which cycle occurs where. It is certainly accurate enough to run an unmodified NIBL though slightly speeded up (4800baud terminal instead of 110. i.e. 21.82MHz. This wasn't just done for the sake of it but to make for a baud rate that the PC would understand)

What I've still not attempted is to do any of the bus-control stuff NENIN/NENOUT etc nor have I attempted to get the timings of the bus access nADS, nWR, nRD accurate - they all take 2TC at the moment. If there's interest I could have a look at this.

This was really just a learning experience for me and a chance to experiment with some microcode/processor control logic. The stuff is all there on GitHub if anyone wants to play with it or to join in! There's probably quite a lot that could be done to make it smaller/faster/better!

I've got it running on a Waveshare development board which holds a Cyclone IV EP4CE10 FPGA and I've been using a PL2303 UART->USB to interface to the PC as a terminal emulator.

Is there a "favourite" NIBL program that I should try running on this to exercise it?

D
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Old 5th Dec 2021, 8:46 pm   #2
Mark1960
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Default Re: A new Verilog core SC/MP - checking against real timings

Very interesting project, I’ve searched a few times to see if anyone created an scmp core in verilog or vhdl, but I think yours is the first.

When you refer to TC, is this equivalent to microcycles of the INS8060 or is that clock cycles. I think two microcycles for each memory access is correct.

I wonder how many Scmp you can run in a cyclone IV if you did have NENIN/NENOUT working. You could probably also run it at more than 100MHz.
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Old 5th Dec 2021, 9:16 pm   #3
Timbucus
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Default Re: A new Verilog core SC/MP - checking against real timings

Nice progress well done - I have not really played with Verilog.

Mark - there was one as part of DAVER2's (VCFED) MK14 which I got running on my Spartan 3 board - it had some issues and would not run all MK14 programs. This also included the VDU for that device. I adapted it so that it would allow use from Sirius PI programmer as the built in key interface was clunky using a rotary encoder.

https://www.vcfed.org/forum/forum/ge...14=#post852955

This was linked in the original thread from Dominic (so a pretty obscure route no wonder you missed it):

https://www.vintage-radio.net/forum/...d.php?t=167311
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Old 6th Dec 2021, 12:39 am   #4
Phil__G
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Default Re: A new Verilog core SC/MP - checking against real timings

Sounds fascinating Dominic
Quote:
Originally Posted by dominicbeesley View Post
Is there a "favourite" NIBL program that I should try running on this to exercise it?
If you download the PICLV2 document (PICLV2files.zip) there are several NIBL demo programs in there for copy-&-paste, including the BASYS monitor written in NIBL. The Calendar keeps it pretty busy. Its on http://philg.uk

Your FPGA scamp might be the answer to a 32k system running Karen's PAGE2.SYS
Cheers
Phil

Last edited by Phil__G; 6th Dec 2021 at 12:48 am.
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Old 6th Dec 2021, 2:23 pm   #5
dominicbeesley
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Default Re: A new Verilog core SC/MP - checking against real timings

Thanks all for the replies,

Mark, Re the TC thing I thought I'd understood it but then my system ran at 880 baud when the cpu clock was at 4MHz when I was expecting it to do 440 baud! I need to have another read of the datasheets!

Each verilog cpu_clock executes one micro-cycle which I think corresponds to TC? i.e. the when I'm running at 4MHz its like an NMOS running at 8MHz?

Timbucus, I'd forgotten that but have just reacquainted myself with it. So far I've gone for a very minimal test rig which just consists of RAM on add 4k banks on ROM on the first two even ones. I've not tried out anything other than NIBL. The serial port is very simple just RX connected to SB and TX connected (inverted) to F0, no flow-control or anything else.

Thanks Phil, I'll try some of those programs. I have to admit to being a bit lost as to what PAGE2.SYS does! (I actually know very little about all this stuff and haven't had the time to digest all the many Mk.14 threads!)

I will have a look at how fast/small I can get this going first (I did this in an exercise in honing my Verilog/FPGA skill). Quartus is reporting an FMax of
approx. 53MHz but I suspect that can be increased if I have a look at how the memory is being accessed.

I'd quite like to have a go at a Mk.14 clone maybe with VDU but will have to get my head round how it should work!

D
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Old 6th Dec 2021, 4:22 pm   #6
Mark1960
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Default Re: A new Verilog core SC/MP - checking against real timings

From the 8060 datasheet TC is twice the clock period and a microcycle is 2x TC.

Each memory access takes two microcycles. The microcycles for each instruction is a little clearer in the original pmos 8060 technical manual, though I was a bit confused about which cycle the PC is incremented as the instruction fetch is shown as the first two microcycles and The PC should be incremented first.
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Old 6th Dec 2021, 4:25 pm   #7
Mark1960
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Default Re: A new Verilog core SC/MP - checking against real timings

The easiest way to add the MK14 vdu might be to use schematic capture in quartus, though it might make it less portable than verilog. I think there is a way to generate verilog or vhdl from schematic capture, but its been a few years since I played with fpga.
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Old 7th Dec 2021, 2:17 pm   #8
dominicbeesley
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Default Re: A new Verilog core SC/MP - checking against real timings

I'll have a look at the mk14 I really don't know much about the mk.14. I'll probably do everything in Verilog. I'm not sure how well, if at all, schematic capture work in the simulator and last time I tried schematic capture I found it slow, fiddly and annoying though that was a will ago.
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