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Old 12th Dec 2018, 9:08 am   #41
trsomian
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

Interesting to note that the computer PSU example shown also uses proportional base drive, which eases the load on the driver transistors somewhat quite apart from decreasing the switching losses.

As with any transformer, one obviously has to ensure that average volts seconds applied is zero, or saturation will result; not so easy if extreme MSRs are required.
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Old 12th Dec 2018, 2:40 pm   #42
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

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Originally Posted by Argus25 View Post
One other trick they did, since they use BJT's as the output devices and not mosfets, they ran the output connection around the transformer core, so as the output power and current increases, it reinforces the base currents of the output transistors which makes sure the transistors stay saturated as the collector current increases and makes it more efficient across a range of output loads, but not enough + feedback that it oscillates.
Proportional base drive. In fact there is much more than enough feedback to make the thing oscillate.

When you want one of the power transistors Q1 or Q2 to turn 'on' you make sure that one of Q5 or Q6 are 'off'. If both are 'off' the thing would oscillate, at a frequency determined by how long it takes the drive transformer to saturate (which would kill the drive; the thing would then flip states). But until that point, the power transistor gets fed with base current according to the turns ratio on the drive transformer - if the base winding is 20 turns and the feedback winding is 2 turns, then you drive the base with 1/10th of the collector current. Low collector current and you just get a bit of drive. Large current and you get a lot. Simple and elegant.

Well before it would self-flip states due to drive transformer saturation, though, the 3524 control IC terminates the drive by switching Q5 and Q6 both 'on'. The primary of the drive transformer is then virtually short-circuited, so gobbles all the current reflected from the feedback winding. The base drive disappears and the associated power transistor Q1 or Q2 turns 'off' - in fact stored charge is rapidly sucked out of the base due to the voltage on C16 or C17 taking Vbe about 1.4V negative. This state of affairs continues until the control IC decides it's time to turn on the other power transistor. It turns 'off' Q6 or Q5 (whichever one it's its turn to be), accordingly a small current has to flow into from R14 or R17 into the primary of the drive transformer. This is added to a small current remaining due to stored energy in the core, and supplies base current to the relevant transistor Q1 or Q2. It starts to turn 'on', collector current flows, and regenerative action quickly takes place magnifying the base current until the transistor is hard 'on'.

What is important to note is that it's not just a bit of feedback - it's a lot! I designed a single-ended version of this for a flyback converter which is in regular use. It's simple, and it's very low-loss. It does make for a more complex drive transformer, but that happens to be a lot of my 'day job' anyway!
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Old 12th Dec 2018, 10:20 pm   #43
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

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Proportional base drive. In fact there is much more than enough feedback to make the thing oscillate.

- if the base winding is 20 turns and the feedback winding is 2 turns, then you drive the base with 1/10th of the collector current. Low collector current and you just get a bit of drive. Large current and you get a lot.

What is important to note is that it's not just a bit of feedback - it's a lot! I designed a single-ended version of this for a flyback converter which is in regular use. It's simple, and it's very low-loss. It does make for a more complex drive transformer, but that happens to be a lot of my 'day job' anyway!
In this circuit though, that auxilialry winding (see pg 7 of the article) is just two turns of wire wrapped around the bobbin. The current in this wire is simply proportional to the power supply's output current, which is very low with low loads.

I don't know what the exact turns ratio is (with respect to the base drive windings), but the amount of + FB here only becomes significant at high loads. If the drive to this output stage is switched off (the SG3524 inhibited) at any load, the output stops immediately with no self oscillations. Which is why I mentioned that the stage (or this feedback arrangement) doesn't have enough + feedback, due to this winding, to self oscillate.

One issue with a BJT output stage, is that the ideal base currents and base drive power dissipation, for the supply running at full load, are much higher that what is required for a low load. This feedback improves that issue, but it cannot be high enough that the circuit self oscillates even on full load, if it did the pulse width modulated control drive, from the driver (SG3524) would lose control and the output go to max.
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Old 12th Dec 2018, 10:48 pm   #44
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

MOSFETs are well-known for turning on at the slightest hint of gate-voltage. Good designs include bleeder resistors.

This was a big problem with some of the early CMOS logic [4000-series] chips - if you left unused inputs floating rather than tied-down it was quite common for leakage across the PCB to cause the logic to be biased into the linear region of operation. At which point the 'low power' portable digital-device design you were expecting to draw only a few microamps could start drawing 10mA or so, leading to customers becoming deeply unimpressed when the batteries repeatedly ran flat after days not your predicted 'several years'.
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Old 12th Dec 2018, 11:12 pm   #45
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

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The primary of the drive transformer is then virtually short-circuited, so gobbles all the current reflected from the feedback winding.
I agree with this too, it would require that both the SG3524 outputs go high when the SG3524 is inhibited too, so that both the driver transistors are switched on, then there would be enough damping to stop the oscillations due to the feedback winding. I guess the only way to find out if there is enough feedback for self oscillation would be to disconnect the primary winding, which is an experiment I have not done. If it does self oscillate under that condition, it makes it a worrying design to some extent in that if one of the drive outputs disappeared from the SG3524 or a driver transistor went open circuit, the circuit could oscillate to a 50% duty cycle and produce high output voltages on the supply's output causing major destruction to what it powered, even if the shutdown (voltage window) circuit disabled the SG3524 !

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Old 12th Dec 2018, 11:33 pm   #46
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

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MOSFETs are well-known for turning on at the slightest hint of gate-voltage. Good designs include bleeder resistors.

This was a big problem with some of the early CMOS logic [4000-series] chips - if you left unused inputs floating rather than tied-down it was quite common for leakage across the PCB to cause the logic to be biased into the linear region of operation. At which point the 'low power' portable digital-device design you were expecting to draw only a few microamps could start drawing 10mA or so, leading to customers becoming deeply unimpressed when the batteries repeatedly ran flat after days not your predicted 'several years'.
Another trick is that cmos IC's still can work when you forget to connect their power supply pin (This is mentioned in H&H) The chip is then powered by one of the input protection diodes, so at least one input pin needs to be high to power it. If in some logic state all the inputs are low, the chip then stops!

Another thing, especially in vintage cmos, the output stage of a gate can go completely open circuit, leaving the input/s it feeds floating, then there all sorts of effects depending on the voltage level as the gate capacitances acquire some charge. Then when you connect your scope onto that point it very quickly discharges the gate capacitances and it looks like a logic 0. Though, with a good scope like a 2465b and using the trigger level set for a few hundred mV, the trigger light will flash, giving the game away that there was in fact some voltage there before the scope got connected.
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Old 13th Dec 2018, 10:56 am   #47
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

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If the drive to this output stage is switched off (the SG3524 inhibited) at any load, the output stops immediately with no self oscillations. Which is why I mentioned that the stage (or this feedback arrangement) doesn't have enough + feedback, due to this winding, to self oscillate.
It won't oscillate if the drive is inhibited, because the 'drive' windings are effectively shorted by the drive transistors immediately being both 'on'. So positive feedback is immediately killed. The positive feedback is only active when a drive transistor is 'off'.

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One issue with a BJT output stage, is that the ideal base currents and base drive power dissipation, for the supply running at full load, are much higher that what is required for a low load.
Agree! 'Fixed' drive is for BJT's is wasteful at low loads. You have to hit the transistor with the base current appropriate for maximum load, which is more base current than it needs at low loads. And as you say, dissipation due to base drive (Vbe x Ib) can be significant - even higher than collector dissipation (Vce x Ic)! Plus, excessive base current can add microseconds to the turn-off time.

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This feedback improves that issue, but it cannot be high enough that the circuit self oscillates even on full load, if it did the pulse width modulated control drive, from the driver (SG3524) would lose control and the output go to max.
But a well-designed proportional drive circuit is just that - and it does latch!! It's like a thyristor. Or an Eccles-Jordan bistable. Both have tons of positive feedback. They don't oscillate. They latch.

In proportional drive circuit, there's enough positive feedback that it latches quasi-stably into one of two states (the critical condition is: Base:Collector turns ratio >hfe). If you disconnect the drive winding, it would square-wave oscillate (the half-period depends on the time for the drive transformer to saturate, at which point everything 'lets go'). I've made self-oscillating, unregulated, low power, highly efficient, two-transformer push-pull converters which work well, using just base and feedback windings on a tiny drive transformer core which saturates. The circuit looks a bit like the single-transformer Royer converter, but operates much more efficiently and elegantly. Can't claim originality - Keith Billings (of 'Switchmode Power Supply Handbook' fame) introduced the circuit to me, showing me one he'd built. And I've designed and built regulated versions by adding a drive winding and control circuitry which 'kill' the positive latching feedback at the right instants, so the control circuit has complete control, just like the one in your write-up.
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Old 13th Dec 2018, 12:01 pm   #48
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

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In proportional drive circuit, there's enough positive feedback that it latches quasi-stably into one of two states (the critical condition is: Base:Collector turns ratio >hfe). If you disconnect the drive winding, it would square-wave oscillate (the half-period depends on the time for the drive transformer to saturate, at which point everything 'lets go').
Thanks, a great analysis.

The only thing that concerns me when the feedback is enough to sustain oscillations, is that if there is an anomaly in the drive control circuitry, for example in this case just one driver transistor dropping out the system goes to max output voltage and is uncontrolled.

Another interesting test would be to remove the two turn loop off the transformer to see how it affects the supply's performance. Not all switch mode computer supplies have this loop.
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Old 13th Dec 2018, 6:11 pm   #49
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

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However, I'm dubious about Hug's circuit for the following reasons....

When the driver FET is 'on', no problem - the 20V will be imposed on the transformer primary.
When the driver FET turns 'off', the transformer's inductance and back-EMF will attempt to reverse the voltages on the windings. There can be no current in the primary. But to achieve the target condition - the first FET 'off' and the second FET 'on', as we have seen we need 114mA to be flowing. This can only be the case if there was AT LEAST 114mA of magnetising current flowing at the moment of switch-off.

Hi folks,

A quick update. I built Hugo's driver, only using two N-channel power devices.

I have no qualms about the RHS of the circuit, everything on the secondary side of the pulse transformer.

However, constructing it as shown (only verifying on the scope for signals in antiphase for 2 x N channel transistors) but with back-to-back zeners in the gate, it didn't quite produce the desired result.

I first tried it with the driver MOSFET exactly as shown, but it overheated.

I then tried it with a new biasing arrangement and a new MOSFET, an IRF540. I biased it at 5.5V (using 18K and 12k voltage divider and a 15V8 power supply) the linear part of its transfer characteristic.

I imagined this would be perfect, especially as the MOSFET has an intrinsic body diode, which I thought could deal with the leakage inductance of the transformer. (

However, the MOSFET again failed... well before, I might add, reaching its apparent maximum temp of 175 degrees C!

I undid the primary side of the board and tried a complimentary pair of bipolar transistors to drive the pulse transformer in AB.

However, the output voltage was too low to produce enough turn-on voltage in the secondary. (An annoying thing with push-pull drivers, right, perhaps OT for this thread, but I'm describing the simple and well-known arrangement with no passive components. )

I suddenly realised that if I carried on, the next step in trying 'something different' would be to repeat building the circuit pictured that I've already built, below, either earlier this year or last year. It's from Texas Instruments.

It's also on this YouTube video, a little way in. The narrative isn't technical enough for my liking - and I'm not even an engineer - but there are several solutions described, especially a couple that are rather more complex towards the end.

I built this version (the pic I've upoaded) sometime last year or earlier this year, and found it to be excellent. It is completely isolated, and doesn't even need a DC power supply.

I posted about it at the time so repeating it is unnecessary.

It was designed by TI specifically to do what I'm asking - provide a cheap alternative to bespoke gate drivers for little outlay. Only with any bipolar devices I can find, it's still way underpowered (by a factor of 10 per power device) for the purpose I described at the top of this thread.

Quick note: if using largish caps on the voltage divider, as someone pointed out on the comments in the application page, worth watching for 'first pulse' current when switching on.

Resources and time being finite, I'm going to cap my investigation of Hugo's circuit, at least for the time being, noting that the RHS is tried-and- tested and meets the challenge of a drive architecture using discretes.

However, the jury is out on the LHS arrangement of a device in class A.

Meantime, back to mulling over my options before getting the soldering iron out again.

I note that another way of doing this, used in flyback converters, is to have a MOSFET on the primary side of the pulse transformer. Only, the MOSFET is being hard-switched on with a square-wave drive signal of appropriate amplitude, it's not in class A. There is I mandatorily a clamp circuit to dissipate the energy stored in the pulse transformer's parasitic inductor.
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Old 13th Dec 2018, 6:30 pm   #50
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

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The only thing that concerns me when the feedback is enough to sustain oscillations, is that if there is an anomaly in the drive control circuitry, for example in this case just one driver transistor dropping out the system goes to max output voltage and is uncontrolled.
It would, yes. Which is why lots of power supplies have Over-Voltage Protection, to protect the load. There are lots of mechanisms by which output voltage can shoot up - this is just one.

I have even seen a version of this circuit where the control circuitry is ENTIRELY powered from the main switching transformer, there being no auxiliary mains transformer to start-up, and there are a couple of high-value resistors to the bases of the power switching transistors to bias them 'on' with a milliamp or so of base current. Uncontrolled oscillations start, in the manner that you are feared of, but with the power transformer then giving an output, the control circuit soon establishes itself and takes over. With sufficient inductance in the output filter chokes, the start-up transient never makes it to the load.

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Another interesting test would be to remove the two turn loop off the transformer to see how it affects the supply's performance. Not all switch mode computer supplies have this loop.
You could try this, but be prepared to let the magic smoke out of your power switching transistors!

Which really brings us to Astral Highway's original post. Gate drive - or base drive - circuitry is non-trivial. But having a transformer in there does allow for a several volts of ground bounce, all for free. You can take your drive return lead right back to the emitter or source pin on the device, without making ground loops. You could even carefully 'float' a driver IC such as Al's TC4451 or 4452 on the secondary of the drive transformer, maybe getting its power via a common-mode choke, such that the drive transformer carries the switching edges, and the driver IC supplies the pulses of high current. You can have DC restoration circuitry, to give the right voltage levels as duty cycles approach 0 or 100%.
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Old 13th Dec 2018, 8:17 pm   #51
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

Typo, 5th paragraph, post #49.

18K and 10K in the bias voltage divider , not 12K.
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Old 13th Dec 2018, 8:51 pm   #52
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Hi folks,

A quick update. I built Hugo's driver, only using two N-channel power devices.

I have no qualms about the RHS of the circuit, everything on the secondary side of the pulse transformer.

However, constructing it as shown (only verifying on the scope for signals in antiphase for 2 x N channel transistors) but with back-to-back zeners in the gate, it didn't quite produce the desired result.

I first tried it with the driver MOSFET exactly as shown, but it overheated.
I did say I was dubious! When the drive MOSFET turns 'off', unless the drive transformer has a pretty LOW inductance, there will just be insufficient stored energy within the core to give a decent reverse secondary voltage.

That being so, the flux in the core won't decay much. It'll stay nearly where it was at the end of the 'on' period.

A few more 'on' periods and the flux will have built up to the point where the core saturates. Inductance will vanish, the drain current will shoot up, and the FET will die.

And if the transformer DOES have a low inductance, then drain currents will ramp up fast anyway during the 'on' time, though hopefully not to destructive levels. It's almost a no-win situation.

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I built this version (the pic I've uploaded) sometime last year or earlier this year, and found it to be excellent. It is completely isolated, and doesn't even need a DC power supply.

I posted about it at the time so repeating it is unnecessary.

It was designed by TI specifically to do what I'm asking - provide a cheap alternative to bespoke gate drivers for little outlay. Only with any bipolar devices I can find, it's still way underpowered (by a factor of 10 per power device) for the purpose I described at the top of this thread.
That circuit ought to work! It's an example of a circuit where the drive transformer sends the drive signal, but a secondary-side circuit supplies the 'grunt' to drive the output FET gates.

It's simple! I've played with this sort of circuit. In fact, you can even leave out the BAS16 rectifier diodes which provide the local secondary supply rail. The base-collector junctions of the complementary transistors will do the rectifying for you. However, you may want to use some meaty transistors which can handle high pulse currents. Try Ferranti ZTX850/950.
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Old 14th Dec 2018, 12:34 am   #53
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

Al,

I could suggest if you are going to try a circuit like the one I suggested do not initially fit the output mosfets. Simply get the class A driver circuit working and across each zener diode (where the gate and source connections would be, if the mosfet was in circuit) place a capacitor about equal to the mosfet's gate capacitance. Then you can get the design of the transformer right. Then you can confirm what would be the mosfet gate drive voltages, are correct, before putting in the power mosfets. So I am not surprised it failed to work.
It sounds as though there was inadequate primary inductance and or inadequate core magnetization.

Can you attach a photo of the transformer you made along with its inductances and DC resistances and core type and cross sectional area ?

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Old 14th Dec 2018, 1:11 am   #54
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The only thing that concerns me when the feedback is enough to sustain oscillations, is that if there is an anomaly in the drive control circuitry, for example in this case just one driver transistor dropping out the system goes to max output voltage and is uncontrolled.
It would, yes. Which is why lots of power supplies have Over-Voltage Protection, to protect the load. There are lots of mechanisms by which output voltage can shoot up - this is just one.
Yes, but the over voltage protection is mediated in these power supplies by shutting down the drive (the SG3524) which in case of this failure would be useless. There are no active crowbar circuits on the output capable of clamping the voltage down. This is one reason why I thought it unlikely the circuit could self sustain oscillations in the event of a drive failure. That was the point I was making.
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Old 14th Dec 2018, 8:44 am   #55
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

Most often, a switch mode power supply is worth a lot less than the stuff it's powering. There is always a risk that an SMPS could lose its control feedback and go flat-out, applying a silly voltage to all the stuff downstream. In linear PSUs the series pass transistors can fail shorted and do the same thing. There is the same thing in buck regulators. Crowbars can limit the damage. I'm a big fan of crowbars in the right places.

Someone buys an amateur radio transceiver for a couple of thousand pounds, then shops around for the cheapest 13.8v 30A power supply he can find..... oops! Guess what's not covered under warranty? Been there, seen it: "Er, David, could you fix this?" "Yes, but it'll probably wind up costing more than a new rig"

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Old 14th Dec 2018, 11:35 am   #56
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

Hi Hugo, I’m away from home today and much of tomorrow but indeed, my approach was to build the transformer on a ferrite, and substitute 1n5 pulse caps for each MOSFET on the secondary side before going further.

I built the transformer on a small EPCOS ferrite about 1cm across. In my drive to find the holy grail of pulse transformers for my (bigger picture ) project, I’ve wound tens and tens of experimental gate drive transformers on all sorts of materials over the last couple of years.

I know that minimal leakage inductance is wanted, along with sufficient magnetising current , but not enough to saturate the core. After many experiments , I can now pretty quickly hone in on practical results that work.

But sometimes an extra design consideration pops up . In this case, (as I was using trifilar wire from a cat5 Ethernet cable), the limit imposed by the physical dimensions of the former was 10-11 trifilar turns. I tested this separately (with another power device as the driver ) and it did appear to have promising waveforms all the way up to 500KHz.

However, note that this whole winding has a DC resistance (estimated) of a fraction of an ohm. It’s a short circuit to DC in the drain of the MOSFET in the circuit.

A pulse transformer that would have enough DC resistance (say 15R) to somewhat limit current in the drain of the driver MOSFET would need 100’s of windings of thin wire. It would accordingly be bulky and to be on quite a large former and so its need to give rise to a high resistance to DC would end up giving it far too much magnetising current and leakage inductance, and the core would likely saturate.

This is one reason why I don’t think class A is a feasible mode for this driver. It needs to be on a monumental heatsink and even then, the pulse transformer is going to be a tall order if impossible to design.

Wasting heat seems counterintuitive with this brief. If we’re trying to get the biggest blobs of current flowing in the gate transformer on the side of the power MOSFETs, there’s something discordant about dissipating 15-20W or more in the driver transistor.
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Old 14th Dec 2018, 1:04 pm   #57
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

Hi Al,

From what you have said I think you are right.

It would appear though regardless of the circuit topology, if your mosfets have that high gate capacitance (is it really 24nF ?) that you noted in a previous post and you want the circuit to switch with a fairly rectangular voltage with about maybe 50 to 200nS rise and fall times and an operating frequency around 300kHz, it is a big problem with the high gate capacitance charging current requirement.

With your operating frequency is does seem that transistors would be the way to go, specfically an RF capable power transistor.

For a really decent sharp square wave of 300kHz, the upper harmonic required for that is about 21f, or about 6MHz, and the rise time is about 40nS. But you would still get a "reasonable" square wave with a rise time of 3 or times that around 150nS .

So it seems you would really require large RF capable transistors rather than mosfets, or the driver will be more awkward. I wonder if Kalee20 agrees with that ?
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Old 14th Dec 2018, 1:42 pm   #58
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

Hi Hugo,

Interesting point about the 21st harmonic, although I have had perfectly clean, sharp wavevltems , switching one gate with 7nF capacitance.


Yes, the gates of the blg mosfet bricks have capacitance 24-30nF per gate. Calcs are on post #20 of this thread.

Please remember, though , the transformer and LHS of the circuit we were discussing on this thread is to drive comparatively small MOSFETs with gate capacitances only 1.5-1.7 nF, ‘the driver of the drivers’

I have never seen RF transistors used in this mode. I have seen and trialled and posted on the forum successful switching of a single , very common MOSFET in class E at some MHz. (IRF540 and its bigger relatives are capable in class E to at least 4MHz) The switching waveforms were beautiful but one transistor can’t switch much compared to a half or full bridge .

I have also seen and investigated many designs for half or full-bridge IGBT or MOSFET switches up to HF. They are a lot more fiddly than say switching at 20-60KHz, but it has been done.

It only gets really tricky with the biggest IGBT or MOSFETs with gate capacitances over 20nF, in my experience so far, especially above 200kHz and if we want to avoid heavy power supplies and get a high peak current and close to max possible ave current from a commonly avaialable SMPS!

But plain old MOSFETS can definitely do this.

Options :

1) The TI design could be ramped up with beefier transistors, with two transistors driving each gate to get close to 20A per gate peak drive current

2) The UCC37321 and UCC37322 ICs could have thermal paste applied to their woefully small 8DIP bodies and mounted tight to the PCB, and be paralleled each with another of the same type, avoiding ground loops.

3) New TC4451 and 4452’s could be used again , only with a crowbar in case my voltage regulator fails again .

I haven’t tried option 2) and have some, so am tempted . The advantage of a bespoke gate driver IC is ability to sink reverse currents of some A, as well as immunity from cross -conduction and latchup, great noise immunity and an ENA pin!

Whichever solution works in the end will have a very good pedigree by that stage!
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Last edited by Al (astral highway); 14th Dec 2018 at 1:51 pm.
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Old 14th Dec 2018, 2:26 pm   #59
Argus25
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

1.5 to 1.7nF is more reasonable. In principle I think the transformer drive will work. And I agree class A driver not ideal, better with a 4 transistor bridge and no net core magnetization.

There is one good advantage of the isolation, is that you can also have a voltage step up function. So there is no reason why you cannot have a 5V system (74HC or HCT logic) on the primary driving the bridge. Then you could keep the drive circuitry elegant with say the complimentary output of a flip flop (clocked at 2f) driving the bridge circuitry on the transformer primary side.
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Old 14th Dec 2018, 2:31 pm   #60
Argus25
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

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