Manor Supplies Cross Hatch generator MK2

[KeithsTV]

I built a simple 405 line pattern generator to generate a cruciform pattern several years ago. Initially I used 555s to generate the line and field sync frequencies but found that it was very dificult to set the field frequency to exactly 50Hz, setting the line to 10.125kHz was no problem. I ended up using a 555 running at 20.25kHz (twice line frequency) and dividing down to generate the line and field frequencies. I also have to admit to using monostables to generate all the necessary pulses for the syncs and signals. (I am doing penance for using them but in my defence it was a quick and dirty circuit built in a few hours to test a TV)

Generating the sync pulses in this way has the advantage that the line and field are locked together and there is only one adjustment needed to set them. It's easier and quicker to accurately set a 555 oscillator to 20.25kHz than to set one to exactly 50Hz in my experience.

Keith

[ppppenguin]

Worth noting how hard an SPG was until integrated logic was available.

Pre-war, the main options were mechanical (think Hammond tonewheel organ) or chains of locked oscillators acting as frequency dividers. This was the reason that line count needed to be factored into SMALL integers. Locked oscillators are not very good at large ratios, tending to lock on to the wrong divisor.

Postwar, it could be done with valve binary dividers and logic but that's a lot of valves. Transistors could be used in the same way, with corresponding power and size reduction. One Pye SPG, perhaps others too, used tapped delay lines for all the line rate stuff.

I think the BBC designed an SPG using early ECL logic chips. Once TTL arrived things were much easier. Programmable logic makes the basic design very easy. Starting with a suitable master oscillator you can write a simple SPG in a few tens of lines of VHDL. I've clipped some fragments of code from a recent design, actually part of a PAL/NTSC coder to show what's involved. This shows most of the mixed sync generation. Clock is 54MHz which was conveniently available and no problem for the device I was using.

-- Central horizontal 13 bit counter. Half line length up to 1728 pixels. Keep 13 bit counter for convenience.
        if HRESET then HCOUNT <= 0;                            -- Reset at terminal count or master reset
            else            HCOUNT <= HCOUNT + 1 mod 8192;    -- MOD not essential for symthesis but vital for simulation
        end if;


        MS_START <= (not SD_EQ_EN and (HCOUNT = SD_H_OFFSET) and HMULTIPLE(0) = '0')    -- Line sync on whole lines only
                         or (SD_EQ_EN and (HCOUNT = SD_H_OFFSET));                                    -- EQ and BP on half lines in field interval

        MS_END <= (not SD_EQ_EN                  and (HCOUNT = SD_H_OFFSET + SD_SYNC_WIDTH))    -- Sync pulses (4.7us)
                      or (SD_EQ_EN and not SD_BP_EN and (HCOUNT = SD_H_OFFSET + SD_EQ_WIDTH))        -- EQ pulses (2.35us)
                      or (                 SD_BP_EN and (HCOUNT = SD_H_OFFSET + SD_BP_WIDTH));        -- Broad pulses (27.3us)

			if  MS_START then MIXED_SYNC <= true;	-- JK flipflop
			elsif  MS_END   then MIXED_SYNC <= false;
			else                 MIXED_SYNC <= MIXED_SYNC;
		end if;


        if VERT_CE then
            SD_EQ_EN_START <= (PAL and (VCOUNT = SD_V_OFFSET + 3))
                            or (NTSC and (VCOUNT = SD_V_OFFSET + 2));
                            
            SD_EQ_EN_END <= (PAL and (VCOUNT = SD_V_OFFSET + 18))
                          or (NTSC and (VCOUNT = SD_V_OFFSET + 20));
                    
            if        SD_EQ_EN_START then SD_EQ_EN <= true;    -- JK flipflop
                elsif  SD_EQ_EN_END   then SD_EQ_EN <= false;
                else                       SD_EQ_EN <= SD_EQ_EN;
            end if;                

-- SD Broad pulses. 5 half lines for PAL; 6 half lines for NTSC                        
            if PAL then SD_BP_EN_START <= (VCOUNT = SD_V_OFFSET + 8);
                else     SD_BP_EN_START <= (VCOUNT = SD_V_OFFSET + 8);
            end if;
                            
            SD_BP_EN_END <= (PAL and (VCOUNT = SD_V_OFFSET + 13))
                          or (NTSC and (VCOUNT = SD_V_OFFSET + 14));
                            
                    
            if        SD_BP_EN_START then SD_BP_EN <= true;    -- JK flipflop
                elsif  SD_BP_EN_END   then SD_BP_EN <= false;
                else                       SD_BP_EN <= SD_BP_EN;
            end if;

[pichacker]

-- SD Broad pulses. 5 half lines for PAL; 6 half lines for NTSC
if PAL then SD_BP_EN_START <= (VCOUNT = SD_V_OFFSET + 8);
else SD_BP_EN_START <= (VCOUNT = SD_V_OFFSET + 8);
end if;

Doesn't this do the same either way??

I too have been through the TTL/Monostable routes to uP control in my days of Macro removing so I could distribute programms through my VCR.

We've only to look at the excellent Aurora to understand how things have progressed.

[ppppenguin]

Well spotted, indeed it is the same in PAL and NTSC. At the time I started writing the code I wasn't sure that it would be the same on both standards. I felt it was clearer to leave the explicit code for both standards. I have enough trouble understanding my own code at the best of times so anything to help me help myself The compiler optimises out any excess logic.

I also often put in the "do nothing" or "hold" condition for a counter or other logic even though it's implicit in VHDL. Again just to make it clear to myself that nothing is meant to be happening. For example:

if RESET then MYCOUNT <= 0;
elsif COUNT_ENABLE then MYCOUNT <= MYCOUNT + 1;
else MYCOUNT <= MYCOUNT;
end if;

[terrykc]

Originally Posted by dragonser

I used some online design tools for the 555 and this suggested that for 405 line operation a cap value of about 1n2 could be used in place of the 820pf cap. But I think your calculations are more accurate.

This agrees with my original comment about increasing the value of C1 by 50% ...

I'll try a 1% 68k resistor and check the frequency that is produced.

Why? There is nothing wrong with the existing resistor and, when combined with a 22k in place of the 18k, actually does you a favour!

If you look at the attached spreadsheet (you'll have to unzip it first as that was the only way I could upload it) you can experiment.

The 'Nominal' column calculates the timing based on the data sheet formulae. The 'Adjusted' column shows the timing relationships when the frequency is adjusted to the correct value. The specified values are in the next column, for comparison, and the final column calculates the difference between the specified and adjusted columns.

Changing the values in the green boxes allows you to see what happens with different configurations.

I've used your 71.4k value with 22k. Look at the accuracy and, if you change the 22k to 21.5k, you'll see it improve even more!

Changing to 68k degrades the timing accuracy and, if you also enter the original 18k you'll see it get even worse!

It is easy with even the cheapest DMM to measure resistors with high accuracy. Capacitors not so easy! However, you can see that, by varying the capacitor value, the timing relationships remain fixed, so resistor selection is all you need be concerned with.

There are separate calculations for 405 lines and you can see that, just by changing the capacitor, the timing accuracy between 405 and 625 is very much the same.

Note that I've left it up to you to determine if any set of values is within the available range of adjustment - keeping C1 = 820pF gives the same 405 line accuracy as 1200pF but the nominal frequency is far beyond the adjustment range!

As you still have the video board to deal with, I've added some extra boxes at the bottom for you to add new timing or frequency information - but note the warning message!

[terrykc]

Originally Posted by KeithsTV

... I ... found that it was very dificult to set the field frequency to exactly 50Hz ...

Perhaps you should have restricted the adjustment range? If the adjustment facility was similar to that in dragonser's design, for example, two suitably chosen resistors at either end of the pot would have restricted the adjustment rage considerably.

The alternative, of course, is to use a multi-turn pot ...

[Paul Stenning]

I designed a test pattern and colour bar generator for Maplin Magazine back in 1997, using the SAA1043 sync generator IC and the TEA2000 colour encoding IC, together with pattern generation circuitry using CMOS dividers and logic. It is an updated version of a project I originally designed for Electronics In Action magazine in 1994.

The main ICs and some other parts are now obsolete so I wouldn't advise anyone to try building it now. However I have uploaded a scan here (5.7MB PDF).

[ppppenguin]

Ah yes, the SAA1043. I've used it a fair bit, including in professional designs, along with its companion subcarrier chip the SAA1044. It needed a slightly raised voltage to guarantee it would work corectly. This could be as low as 5.7V which meant it could interface to ordinary HCMOS without problems. Also all pulse timings were rounded to the nearest 200ns (5MHz master clock) so for fully accurate pulse timings I finessed things a bit using both edges of the clock to get the 4.8us line syncs down to 4.7us.

[Steve_P]

Still plenty about.

http://www.littlediode.com/components/SAA1043.html

The other chip is available here:

http://www.littlediode.com/components/SAA1043.html

Cheers,

Steve P.

[terrykc]

I think that second link should be:

http://www.littlediode.com/components/SAA1044.html

[dragonser]

Hi,
sorry for the delay in replying, it has been a busy week !
attached is one photo of the insides.
in reply to the questions, I decided to change the 68k resistor as it was the only one that was at the edge of it's tolerance and also because the line frequency wouldn't adjust to 15khz [ approx ] when measured on a frequency counter. [ it was too low ].
But I will try the unit out with a B and W portable [ 625 line ] and see what the actual picture looks like.
regards Peter

[ppppenguin]

Here's a PAL SPG I made some years ago using SAA1043/1044. Produces all standard pulses plus subcarrier. Not sure what all the other chips are doing on the left PCB. The other PCB contains output buffers/distribution amps that convert the pulses to 2Vp-p into 75R with nicely shaped edges. The PSU and frame are ex-Michael Cox Electronics; a great chassis form for improvising new designs.

It worked last year when I tried it after many years sitting in the garage.

Shown here as a demo of what's possible with those chips. Not sure I want to keep it so may offer it for sale soon.

[bobbyball]

I still have one of these up in my Dad's loft, still half built...!!

Robert

[dragonser]

Hi,
I've scanned in another page, so will upload it here. I did try the generator with the old black and white portable, but I found that when I tuned in the signal there was a lot of noise [ snow] over the image. the normal tv channels seem to be ok. the only way to be sure of what is happening is to try the video output. this will have to wait as the composite monitor I have isn't easily accessible.

[dragonser]

Hi,
well I'm going to try things out with the original design, and then probably modify it. I now have another modulator ( uhf ) from an old vhs video recorder that wasn't repairable. So I can try this out and see what results I get.
the comments about using a 20khz timer and dividing it down are very useful.
20khz is about the frequency needed for 819 lines as well !
regards Peter B

[Peter.N.]

I built one of these when they were current but never did get it to work properly.

Peter

[Lodgesound]

Tektronix composite SPG / TSG's that were telephone numbers price-wise during the early 1990's can now be bought relatively cheaply - I own several which lock my studio together and find them both accurate and extremely reliable.

Often worth re-capping the switch-mode PSU's in them if it has not already been done to avoid anything nasty happening.

[dragonser]

Hi,
al last I am going to check a few things out about the original design. I "think" I may have found a bug in the original design, as soon as I get a scope onto various parts of the circuit I will let you know...
thank you for all your help, Peter B

[dragonser]

Hi,
After using a scope and managing to get myself quite confused, I think I may have found a bug ? After looking carefully at the construction notes provided and also because of other comments on this forum about modulators, it seems that:
1. If the video output is used then the unit should work as expected.
2. If the uhf output is used then tuning in the television doesn't seem to be easy. This seems to be because although the video output signal is reasonably standard, from looking at the uhf modulator [ circuit attached ] it seems to be giving a positive modulated signal !
It was the comments by someone else on this forum that said that one of the Astec modulators needed a negative going video signal that gave me the clue...
I think I had better go and have a cup of fruit tea !
Regards Peter B

[terrykc]

I'm not sure about that as you haven't given your reasoning.

However, it looks to me as if the +ve going video signal is applying forward bias to the transistor which, if the conditions are right, should reduce the gain, which is what is wanted for negative modulation!

It is the same as forward AGC - a subject over which I had a blazing row many years ago with a manager who said such a thing was impossible. (He had a university degree and I hadn't which, in his eyes, made him right by definition!)

He had to climb down the following day when I presented him with a copy of Mullard Technical Communications which explained the process in detail!

This was over 50 years ago when transistors were just coming into use in TV IF strips - when he was studying, transistors hadn't really got past the AM radio stage where reverse AGC was used.

The difference is that reverse AGC pushes the transistor into its non-linear region - fine for a AM radio but the distortion products between the ranges of signals present in a wideband TV channel would render the signal unusable, whereas forward AGC (bias) pushes the transistor further into the linear portion of its characteristic whilst also reducing the gain.

I hope that helps clear up any confusion ...