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Old 30th Jun 2020, 11:59 am   #81
dominicbeesley
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Default Re: SC/MP timing and microcode information

I dug out my PIC stuff for the first time in over 5 years and installed the latest MPLAB IDE thing - which is a lot better than I remembered it being! (I made a Nintendo to Amiga joypad converter for my daughter as her 5yo fingers struggle with a joystick).

I might poke my head into using a PIC for USB serial, if I have a device capable of it in my box-o-chips just out of curiosity. The last time I did any USB on PIC it was all quite faffy and low level. But that must have been around 2003 and I was making a custom driver on the PC end too - so things may be easier? I have no idea where to start yet but will see how I get on for time!

D
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Old 30th Jun 2020, 4:02 pm   #82
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Default Re: SC/MP timing and microcode information

I had a go this afternoon and got a bit further but I now realise where the problem with the echoed characters is coming in....interrupts time.

I have also realised that annoyingly the read relay isn't activated while a program is running so with flow control enabled I can't stop the running program!

I'll report back later.
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Old 30th Jun 2020, 6:02 pm   #83
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Default Re: SC/MP timing and microcode information

Well, I'm a 100% official idiot.

I turns out my simplistic first attempt did work, what had been staring me in the face all the time was that the echoed characters have the top bit set!

The simplistic approach only works when on a board with more than one serial port so I need to look at the options for using a cheaper Arduino, either software serial or my OTT interrupt driven stuff

I've got to go and do other stuff now but will try and post something useful up later this week.

What I propose on the flow control is to make the Arduino respect flow control unless the pending character is a ^C in which case it will either:

if the relay signal is active: send normally
if the relay signal is not active: hold the RX line low until it gets either the RELAY signal

Sound like a plan?

D
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Old 30th Jun 2020, 6:09 pm   #84
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Default Re: SC/MP timing and microcode information

As you may or may not know there is an Arduino library for software-serial I/O on any I/O pin, although I think there is a limitation that when there are two such ports only one can receive at any one time. However I don't think this applies when you use the hardware UART plus one software-serial port.
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Old 30th Jun 2020, 6:56 pm   #85
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Default Re: SC/MP timing and microcode information

Yes, I tried software serial but NIBL echoes each bit as it is received so that is out.

I've basically written my own interrupt SoftwareSerial which seems to work.

Now some questions:
- is there a good source of NIBL BASIC programs anywhere I could test against
- is there a limit on the number of characters in a NIBL BASIC line, whenever I get to character 74 NIBL just enters the line

D
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Old 30th Jun 2020, 7:35 pm   #86
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Default Re: SC/MP timing and microcode information

I wouldn't be surprised if lines we Re limited to 72 chars +CR +-LF as this was common convention in the 70s dating back to punch cards that allowed 72 chars plus an eight character sequence no.
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Old 30th Jun 2020, 8:13 pm   #87
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Default Re: SC/MP timing and microcode information

Quote:
Originally Posted by Slothie View Post
I wouldn't be surprised if lines we Re limited to 72 chars +CR +-LF as this was common convention in the 70s dating back to punch cards that allowed 72 chars plus an eight character sequence no.
Yup....

Code:
    1367/     7BB : CD 01                       ST      @1(P1)          
;PUT CHAR IN LBUF
    1368/     7BD : AA E7                       ILD     CHRNUM(P2)      ; 
INCREMENT CHRNUM
    1369/     7BF : E4 48                       XRI     72              
;IF=72,  LINE FULL
    1370/     7C1 : 9C B3                       JNZ     GETL1
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Old 30th Jun 2020, 8:23 pm   #88
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Default Re: SC/MP timing and microcode information

Quote:
Originally Posted by dominicbeesley View Post
- is there a good source of NIBL BASIC programs anywhere I could test against
I would suggest an interesting one for you may be the April 1979 Practical Electronics Micro-Bus (Page 47) which has one by Nick Toop of SoC which is a program to help diagnose faults on a Microcomputer Kit (the Mk14 of course).

https://worldradiohistory.com/UK/Pra...9-04-S-OCR.pdf
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Old 30th Jun 2020, 10:40 pm   #89
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Default Re: SC/MP timing and microcode information

Thanks all,

I'll keep poking around - I was hoping for a large easy to cut and paste listing but I suspect that is asking too much.

I'll have a read of that article!

D
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Old 14th Jul 2020, 4:01 am   #90
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Default Re: SC/MP timing and microcode information

I've been trying to understand the SC/MP bus sharing protocol. I've never really given this any consideration before because I've never had need to make use of the SC/MP's bus sharing capabilities. I thought I'd share my thoughts on this thread because Dom is going to need to fully understand this in order to create a faithful emulation.

Perhaps you've already grasped all this, Dom, in which case you can enlighten me Otherwise, perhaps we can pick it apart and nail down our understanding.

The BREQ signal seems to work like a semaphore insofar as a contender for the bus checks whether it's asserted then, if not, asserts it. This is NOT bullet proof. Without some diversity in polling it is easily possible that multiple devices may assert this signal thinking that they have won the bus. Collision!

The NENIN/NENOUT forms a daisy chain which assigns priority to devices. A device up stream of the chain can deny devices downstream.

What concerns me is that the SC/MP has the means to abort a memory cycle if it finds itself suddenly denied the bus through NENIN. Is that part of the protocol or a failsafe?

If an SC/MP finds itself being interrupted before finally completing a memory cycle to its satisfaction, how's hardware going to react if it gets several reads or writes? That could cause state desynchronisation if the repeated cycle (some perhaps partial) causes hardware state changes.

So much of this baffles me...
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Old 14th Jul 2020, 8:22 am   #91
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Default Re: SC/MP timing and microcode information

My understanding is that busreq only provides the request for bus access and a new request can not be made if a request is already in progress, but the actual grant of the bus requires nenin to be activated via the priority chain before the bus access begins. Even if two devices make a simultaneous request, only one will have nenin activated.

I saw there are also a couple of instructions that read and then write to the bus without releasing the bus, but i forget which ones. These would be useful as a semaphore between processes.

I think it would take some special glue logic to revoke nenin before a bus cycle is completed, this is something I want to experiment with, even if only to verify the function. As you already mentioned this could cause problems if nenin is revoked after the beginning of nrds or nwds, but should be ok if nenin is revoked during nads. Maybe special care is needed if the halt flag is being decoded.
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Old 14th Jul 2020, 11:28 am   #92
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Default Re: SC/MP timing and microcode information

Thanks both,

I've not quite got as far as verifying this yet - I'm hoping that by slowing the cpu sufficiently I can first work out how the signals relate to the clock and then go from there. The datasheets aren't bad but they are pretty vague about how the clocks work and I'm worried that anything I do will risk meta-stability? Maybe because the SC/MP takes so long to get its act together at the start of a cycle there's enough time for all the logic to settle, and it's all just un-clocked there's enough time before anything is sampled to not have to worry (too much) about any problems of meta-stability?

I've got a bit sidetracked by other projects (as usual) but I'm slowly working away at getting the core cpu to work - I can run small programs so far - but I'll probably need a more robust setup than my big mess of dupont cables to test this out reliably!

It certainly looks like there might need to be some external glue logic around the arbitration process but I've really not thought that through yet. I would be very interested on any thoughts in that direction. I will need to work myself up to building a set of eurocards or similar to make a small multiprocessor system - I'd really like to wire-wrap it all but I've run out of wire-wrap sockets and they are becoming a tad expensive!

As to the read-modify-write instructions I need to have a look at how this is done - whether both breq and enout get held or just breq. I also need a bottle of wine and an hour in a darkened room with a cold flannel on my head to work out how I'd get a multi-processor system to boot up without tripping over itself!

D
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Old 14th Jul 2020, 4:27 pm   #93
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Default Re: SC/MP timing and microcode information

This is still very much a work in progress but I'm planning to make a SC/MPII module to go into an RC2014 based system. Plan is to add this as a second processor to the z80, or to remove the z80 after programming battery backed RAM and then add a second SC/MPII.

Using the scheme from the SC/MPI application note for a multiprocessor, where a flag output of one processor holds the second processor in reset. The flag output would be set to active low when the first processor is reset, so this holds the second processor in reset until the system is ready to allow it to run. The second processor can then hold the first processor with a flag output through an inverter to the CONT input. One processor has its sense input held high, while the other processor has the sense input held low, and this allows the processors to identify themselves to execute their own code.

RC2014 is based on the z80 bus, so I'm decoding 256 byte page to select /IORQ or /MEMRQ, using a '253 for tri-state outputs. I still need to add some more pullups on controls that float when not active. I'd also like to include a way to disable /MEMRQ for bootstrap using one of the flag outputs, but I need to find one more inverter to drive pin 4 and 10 of the '253.

I've also been trying to work out a method for multiple z80 to try and share access to a bus using similar logic to the SC/MPII using asynchronous logic. Using two bistable latches to determine which is active first between /BUSRQ and /GRQ. This is not tested yet but might spur some thoughts on how the SC/MP generates /BUSREQ.

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RC2014_SCMPII_v1_schematic.pdf

RC2014_SCMPII_v1_layout.pdf
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Old 15th Jul 2020, 3:05 pm   #94
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Default Re: SC/MP timing and microcode information

Another observation: the Mk14 VDU obtains the bus by asynchronously driving NENIN high. That could happen at any point during a cycle. The SC/MP gets no warning. The cycle retry feature must surely play a part in preventing the SC/MP program from crashing.

Maybe the designers took liberties? Perhaps there's a friendlier way to evict the SC/MP?
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Old 15th Jul 2020, 4:02 pm   #95
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Default Re: SC/MP timing and microcode information

That is interesting to know, I'll have to try that out somehow and see what it does. It will likely make the microcode a bit more complicated!
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Old 15th Jul 2020, 8:30 pm   #96
Karen O
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Default Re: SC/MP timing and microcode information

I might be wrong

I've studied the Mk14 VDU circuit, and I can see no request/acknowledge signals. The VDU doesn't appear to sense the state of the SC/MP so that it can time NENIN assertion. It's just straight in with NENIN.

It looks like NENIN has an instant effect in disabling bus drivers.

I'm sure there are better Mk14 VDU experts than I, so please say if I've got all this wrong.
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Old 15th Jul 2020, 10:45 pm   #97
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Default Re: SC/MP timing and microcode information

It certainly looks that way to me too, though it's not completely asynchrouns - it is clocked by xout, it does look to pretty much barge in when it feels like it!

I've got some BBC Micro sound stuff I've got my head in this week but I'll try and rig up a barger-in-er circuit next week and see what the sc/mp does in terms of retrying an operation. I'm guessing it just re-does the last bus cycle be it a read or write? It'll be interesting to see how many cycles elapse after NENIN returns before it gets round to retrying.

Looking at the mk14 vdu it seems to just stop the CPU during the active part of the raster rather than even trying to interleave which seems a tad wasteful of cycles!

D
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Old 15th Jul 2020, 11:15 pm   #98
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Default Re: SC/MP timing and microcode information

I just took a quick look at the timing of control signals on my MK14.

This should probably be done at two different clock frequencies so we can calculate which clock edge triggers the change and seperate the delay for propagation from that edge, but I don't want to mess about swapping crystals and damaging the MK14. This is all using the standard 4,433.618 kHz crystal.

First thing I noticed is just how slow the rise time of NADS. I almost thought it might be open collector, but probably just a weak driver.
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Old 15th Jul 2020, 11:18 pm   #99
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Default Re: SC/MP timing and microcode information

And also the relationship of NADS to NWDS, NRDS, DB2
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Old 16th Jul 2020, 9:51 am   #100
Karen O
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Default Re: SC/MP timing and microcode information

Don't risk damage to your Mk14, Mark. I wouldn't if I had one!

Interesting traces. As you say, NADS looks like it's going to high impedance. The clock duty cycle is further from 50% than I would have expected.
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