18th Jan 2022, 4:24 pm | #21 |
Octode
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Re: The PICL V2 - a development of Karens 2007 original
Size limit for 4 layer board is 50mm x 50mm for $2, so I guess the question should be why Phil’s board was priced at $2 for 5 one time.
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18th Jan 2022, 4:39 pm | #22 |
Octode
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Re: The PICL V2 - a development of Karens 2007 original
I've been using JLC for ages and recently I've had three separate PICL orders from them. All were between £2 to £2.70 per board. I've had some quite large M6802 boards from them at £2.60 each and my Cosmac Elf replicas (7" square?) were only £3 each. I think there must be an expensive option that you've accidentally selected Mike, its easily done...
Cheers Phil |
18th Jan 2022, 5:11 pm | #23 |
Octode
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Re: The PICL V2 - a development of Karens 2007 original
...all delivered prices
Oh, and if you say "yes they can place their logo" its cheaper, and they hide it quite well. |
18th Jan 2022, 7:13 pm | #24 |
Octode
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Re: The PICL V2 - a development of Karens 2007 original
I think you are comparing the price for five, excluding carraige, with the price each including carraige when you order five. Also comparing $ to £.
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19th Jan 2022, 10:07 am | #25 |
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Re: The PICL V2 - a development of Karen's 2007 original
I suppose I should chip in and mention I recieved Phils board ages ago and built it. I haven't found a use for it just yet, but you never know! Its a fab little board, and having the flag LEDs on board makes it easy to make the traditional "led blinker" of the controller world....
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19th Jan 2022, 11:45 am | #26 | ||
Octode
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Re: The PICL V2 - a development of Karens 2007 original
Quote:
Another 'economy factor' is unless I'm in a rush, I usually go for the cheapest delivery option, the one that they hide, or say 'not recommended'. Its barely slower (if at all) and much cheaper. Its not the stereotypical Yorkshireman, its cos I'm retired on a low income so it all helps! Also it galls me to see the courier make more money from my order than JLC do! Quote:
Of all Karens projects I find it the most fascinating - its simplicity appeals to my simple mind - yet it has everything the 1976 SC/MP enthusiast would have wanted - plenty of memory, a monitor & NIBL basic Cheers Phil Last edited by Phil__G; 19th Jan 2022 at 11:59 am. |
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20th Jan 2022, 2:44 pm | #27 |
Octode
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Re: The PICL V2 - a development of Karen's 2007 original
After writing that last post I remembered that back in the day at school we had a RML 380Z that hosted a number of languages including Li-Chen Wang's tiny basic (which is essentially what NIBL was derived from). I started writing a Star Trek program for it, which was a challenge given there is a single array that was essentially just peek-and-poke at physical memory (the '@' operator in NIBL). I wish I had a listing of what I did, it was partially functioning..... I will have to have another go maybe!
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22nd Jan 2022, 1:50 am | #28 |
Octode
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Re: The PICL V2 - a development of Karen's 2007 original
Well I finally finished building the board Phil gave me. Took a couple of tries to get it running thanks to a bad mini usb connector on my serial adapter, and also not setting caps lock, local echo and options for CR/LF. I guess I should really read the manual again before turning it on, but far too impatient for that.
Next step is to try and confirm I can assemble the PIC code and still have it working, then try and understand Karen’s code. That might take a while. |
22nd Jan 2022, 1:58 pm | #29 |
Triode
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Re: The PICL V2 - a development of Karen's 2007 original
Could one of you Gentlemen there in the U.K. get a price for the attached PCB at JLCPCB, please? I'm curious if JLCPCB will honor the 'special' 100x100 mm PCB pricing in the U.K., as they do here in the U.S., with boards that have a 4.0-inch (101.6-mm) dimension.
TIA. Cheerful regards. |
22nd Jan 2022, 3:28 pm | #30 | |
Triode
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Re: The PICL V2 - a development of Karen's 2007 original
Quote:
While studying Karen's source code, I've found it helpful to include the macro generated code in comment lines. Example below. Regards... Mike Code:
; Execute SCMP instruction (19) ; NB PCLATH must be set to HIGH OPVEC ; XHALT XPPC0 XNOP EXEC INCPC ; increment program counter | ; | INCF P0HI,F ; (1) | ; | INCFSZ P0LO,F ; (2)(1) | ; | DECF P0HI,F ; ~ (1) | MOVF P0HI,W ; get address hi (1) | ANDLW B'11110000' ; ROM ($0000..$0FFF)? (1) | skpnz ; no, skip, else (2)(1) | GOTO L8 ; branch (ROM) ~ (2) | 7/8? ; ; get opcode from RAM (used as index into opcode vector table) ; RDRAM P0HI,P0LO ; | ; | movf P0LO,W ; (1) | ; | movwf PORTC ; address lo lines (1) | ; | movf P0HI,W ; (1) | ; | iorlw B'11100000' ; /CS1 = 1, /OE = 1, /WR = 1 (1) | ; | movwf PORTD ; address hi + control (1) | ; | andlw B'01011111' ; /CS1 = 0, /OE = 0 (1) | ; | movwf PORTD ; read RAM (1) | ; | nop ; " (1) | ; | movf PORTB,W ; WREG = RAM byte (1) | ; | bsf PORTD,5 ; /OE = 1 (1) | ; | bsf PORTD,7 ; /CS1 = 1 (1) | MOVWF PCL ; jump (opcode vector table) (2) | 20? ; ; get opcode from ROM (used as index into opcode vector table) ; L8 RDROM2 P0PT1,TMP,HIGH OPVEC ; | call P0PT1 ; RDROM1 P0HI,P0LO (2) | < 16F18877 code > ; | movf P0HI,W ; ROM address hi (1) | movf P0HI,W (1) ; | addlw NIBL/256 ; set address hi & 'page' (1) | addlw NIBL/256 (1) ; | movwf PCLATH ; for GOTO or CALL ops' (1) | movwf FSR0H (1) ; | movf P0LO,W ; ROM address lo (1) | movf P0LO,W (1) ; | movwf PCL ; return opcode ($00..$FF) (4) | movwf FSR0L (1) ; | movwf TMP ; save temporarily (1) | ~ ; | movlw OPVEC/256 ; set address hi & 'page' (1) | movlp OPVEC (1) ; | movwf PCLATH ; for GOTO or CALL ops' (1) | " ; | movf TMP,W ; opcode used as vector (1) | moviw FSR0++ (2) MOVWF PCL ; jump (opcode vector table) (2) | 24 movwf PCL (2) |
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23rd Jan 2022, 11:22 am | #31 | ||
Octode
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Re: The PICL V2 - a development of Karen's 2007 original
Quote:
Li-Chen Wang's original "TinyTrek" for Palo Alto Tiny Basic: http://www.dunnington.info/public/startrek/startrek.asc and the original article: (its the same listing) https://archive.org/details/1976-07-...p?view=theater Quote:
Here's your quote, as usual, mostly delivery charges (to UK). The 'cheapest' option (my favourite!) saves you £10 (this is for a long-standing customer, no 'first order' offers) Last edited by Phil__G; 23rd Jan 2022 at 11:40 am. |
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23rd Jan 2022, 3:54 pm | #32 |
Octode
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Re: The PICL V2 - a development of Karen's 2007 original
The number of boards needs to be reduced from 10 to 5 to get the special pricing.
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23rd Jan 2022, 4:04 pm | #33 |
Octode
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Re: The PICL V2 - a development of Karen's 2007 original
Personally I think the actual manufacturing cost is very cheap, most of the overall cost of the order is carriage!
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23rd Jan 2022, 4:23 pm | #34 | ||
Triode
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Re: The PICL V2 - a development of Karen's 2007 original
Quote:
Would you be willing to discuss PICLV2 hardware and code modifications (publicly or privately)? I've got several ideas but I can't really test them out until my PCB order arrives in a couple weeks. In a nutshell... I'd like to test using a 2-pin Red/Green LED and current limiting resistor directly across the Rx and Tx pins as the Serial I/O indicator. Then I'd like to tie the RAM /CS1 pin to ground and control the RAM just with the /OE and /WE pins. Those changes will free up two pins which could be used to address a 32K RAM. Also, since the new PIC I'm using has 32K (words) of flash memory compared to 8K on the '877 or '877A, I'd like to include your KitBugPlus (KB+) Monitor in flash and load it into RAM at startup. Of course the extra RAM (and PIC flash memory) might provide the opportunity for a "PAGE2.SYS" machine implementation, or used to 'save' and 'load' 4K "pages" to/from flash memory. Finally, I've got simpler Serial routines (see below) and a fixed delay subsystem that supports easily changing the serial baud rate with almost any PIC clock frequency. Please don't be afraid to say "****** off". I understand not everyone has time, patience, or interest in such things. Cheerful regards, Mike Code:
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ; Serial input. Character returned in ACC, EXT, and WREG. ~ ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ RXX call getSer ; |00 HOME EXEC ; |00 ; ; Character returned in ACC, EXT, and WREG. DelayCy() uses TMP. ; getSer ; 9600 baud timing (0.16% error) btfsc PORTE,SERIN ; start bit (0)? yes, skip, else |00 goto getSer ; loop (wait for start bit) |00 bsf PORTE,SERLED ; activity LED 'on' |00 DelayCy(104*usecs/2) ; delay 1/2 bit time |00 movlw 9 ; 8 data bits + 1 stop bit |00 movwf ACC ; bit counter |00 getBit DelayCy(104*usecs-7) ; 104 usecs -7 cycle loop |00 clrc ; assume '0' (1) |00 btfsc PORTE,SERIN ; a '0' bit? yes, skip, else (1) |00 setc ; set to '1' (1) |00 rrf EXT,F ; b0 first, b7 last (1) |00 decfsz ACC,F ; done? yes, skip, else (2)(1) |00 goto getBit ; get another bit ~ (2) |00 rlf EXT,F ; shift stop bit out |00 bcf EXT,7 ; clear bit 7 for NIBL |00 movf EXT,W ; copy RX char to ACC |00 movwf ACC ; " |00 bcf PORTE,SERLED ; activity LED 'off' |00 return ; |00 ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ; Serial Output. Tx character in ACC. Uses EXT & TMP. ~ ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ TXX ; 9600 baud timing (0.16% error) bsf PORTE,SERLED ; activity LED 'on' |00 movlw 10 ; 1 start + 8 data + 1 stop bit |00 movwf EXT ; setup bit counter |00 clrc ; C = 0 (start bit) |00 goto TxBit ; send start bit |00 TxLoop DelayCy(104*usecs-10) ; 104 usecs -10 cycle loop |00 setc ; always shift in a 'stop' bit |00 rrf ACC,F ; put data bit in Carry |00 TxBit movf PORTE,W ; read port |00 iorlw 1<<SEROUT ; set TxPin to '1' |00 skpc ; if data bit = 1 skip, else |00 xorlw 1<<SEROUT ; set TxPin to '0' |00 movwf PORTE ; precise bit timing intervals |00 decfsz EXT,F ; all 10 bits? yes, skip, else |00 goto TxLoop ; send next bit |00 bcf PORTE,SERLED ; activity LED 'off' |00 HOME EXEC ; |00 |
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23rd Jan 2022, 7:10 pm | #35 | |
Octode
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Re: The PICL V2 - a development of Karen's 2007 original
Quote:
I usually group a few designs together to save shipping costs and try to avoid DHL as they keep adding customs handling charges even on orders below the tax threshold. First design is $2 usd for 5 and I think $4 for 5 for additional designs so I tend to make the first item an experimental 5 and then 10 for additional designs. One thing to watch for is that the weight of the order can increase shipping charges when grouping boards in an order. |
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23rd Jan 2022, 7:52 pm | #36 |
Octode
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Re: The PICL V2 - a development of Karen's 2007 original
Hi Mike, as I've always said, if its ok with Karens pals its fine by me, my own approach as a relative newcomer here was one of caution so I tried to do it with minimal changes to Karens work, but its since become clear that everyone seems to approve, so go for it!
Another address line or two would be great, then with 32k, page2.sys would probably be the favourite, although since Kitbug+ and Page2.sys are quite separate, theres no reason not to have both! Its possible someone might not want the complexity of page2, or need page 2 for some other power-on auto-run application, in which case KB+ would handle M/C stuff. KB+ was deliberately kept small, with 32k it could be expanded into a full-blown monitor - but then we're back to Page2.sys! Re the red/green - directly connected, I'm not sure - my CH340G datasheet only says that VOH & VOL are in spec at 3mA so i dont know what you could actually draw from the CH340G on the PICL receive line. Unless you mean via drivers? TBH a PICL transmit LED alone is fine - if theres traffic its lit, if not, there isnt Beware of losing the NIBL 'keyboard interrupt' if tightening or speeding-up the serial routines! Cheers Phil Last edited by Phil__G; 23rd Jan 2022 at 8:01 pm. |
23rd Jan 2022, 10:22 pm | #37 |
Octode
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Re: The PICL V2 - a development of Karen's 2007 original
They aggregate several boards from many customers onto one panel. That's why if you select anything but the default choices it can dramatically increase the cost. It's only recently that the colours other than green have been "free", presumably because volumes have gone up so much.
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23rd Jan 2022, 11:17 pm | #38 |
Octode
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Re: The PICL V2 - a development of Karen's 2007 original
Hi Mike,
if you want to increase the address range you proably want to move /OE and /WE so the higher address lines can be written to the port in a single operation instead of adding extra bit manipulation that might break the cycle timing. It could be possible to use only /WE, and ground both /OE and /CS, though the timing might be awkward. Most bytewide ram the /WE will override /OE. You would need to set up the write address while still in read mode with data bus as inputs to pic. Activate /WE, then set data bus to output data, deactivate /WE and as soon as possible change data bus back to inputs to pic. There is a risk of output contention between pic and ram, so might be chancing damage to one or both. Mark |
24th Jan 2022, 3:42 am | #39 | ||
Triode
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Re: The PICL V2 - a development of Karen's 2007 original
Quote:
Quote:
I hope to test several different possibilities once I have boards. I also spent some time today playing with a new compact (2.1"x3.0") PCB layout, just for fun. If I load RAM with Phil's KB+ Monitor, or any other software, from PIC flash memory during startup I can eliminate the expensive nvRAM chip and use a skinny RAM chip installed under the PIC. Anyway, it's just an idea... More later... Stay safe. Mike |
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24th Jan 2022, 9:21 am | #40 |
Octode
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Re: The PICL V2 - a development of Karen's 2007 original
I think I’ve seen a few projects stacking skinny ram under a 40 pin processor, but not sure I would want to solder the ram, or double stack the 40 pin socket to allow the ram to be in a socket too.
It might be nice to pick a low cost case and design the board to fit the case. I was thinking maybe a 2.5 inch portable disk case but they aren’t really deep enough. I did get a couple of extruded aluminium cases and plan to use those for an INS8060 NIBL project, possibly using a pcb panel to mount switches and leds. |