FET & BJT compound follower puzzle

[Skywave]

As per the attached circuit diagram.

Well, it's a puzzle to me! I can understand Q1 and Q2 acting as a compound voltage follower with the input to Q1 bootstrapped via C3 and R3 to provide a very high input impedance. What I don't understand are the purposes of R4 and especially C2. If Q1 is acting as a voltage follower, surely its drain should be connected direct to Vcc. Moreover, the signal at the drain of Q1 is fed to the emitter of Q2 where it meets a smaller magnitude and a relatively phase-inverted signal from the source of Q1. And that seems to defeat the voltage follower function.

► The thought has crossed my mind that perhaps there is a drawing error: R4 and C2 should be shown as a decoupling network with C2 from the drain of Q1 to 0v.

Since this cct. comes from a highly-regarded source, I am seriously doubting my analysis of the circuit - which is relatively simple.

Any suggestions, anyone?

Al. / Skywave.

[Radio Wrangler]

The circuit has a very high impedance at DC, so the trick is to keep the impedance high at high frequencies, and that means minimal input capacitance.

The JFET has distributed capacitance from the gate to the drain-source channel. So though the source follows the gate, and thereby counteracts capacitive currents, the drain usually does not.

In this circuit Q2 emitter drives the drain of the FT so that it too follows the signal voltage. R4 passes the DC current needed by Q1 while allowing the drain voltage to be driven.

So the whole FET channel has signal voltage on it, so the gate to channel capacitance is bootstrapped.

So the measured input C will be lower than the FET datasheet.

They even wrote 0.25pF on the diagram as a clue.

David

[Skywave]

Thank you, David, for your reply. Your circuit analysis skills are superior to mine, so some of what you have written has be puzzled.

In addition to my earlier thinking, where are the errors in the following thinking:

Imagine C2 is omitted. A signal will appear at Q1 drain: yes?
And that signal will be out-of-phase with the signal at Q1 source, yes?
Then, if C2 is connected as shown, that signal at Q1 drain will try to appear at Q2 emitter, yes?
And that signal from Q1 drain will be not be of a smaller amplitude than that arriving from Q1 source, (R4 and R5 are each 10k), yes?
As to the 'direction' of the signal flowing in C2, surely it matters not if that signal flows from Q2 emitter to Q1 drain or vice-versa: it will still oppose the signal at Q2 emitter, arriving by the direct connection from Q1 source, no? Which returns me to my earlier post.

As for the function of C3, that part I understand: R3 has very, very nearly the same voltage amplitude and phase at both ends.

Al.

[turretslug]

The signal from Q2 emitter is at much lower impedance than that from Q1 drain, so it will dominate and take Q1 drain along with it.

If the input capacitance really equates to around 0.25pF, it should make for a useful LO etc. "sniffer" with minimal detuning.

[jimmc101]

It's easier to understand if you think in terms of currents...
Let the signal current at the source of Q1 be i then the drain current will be -i.
The emitter current of Q2 will be (hfe+1)*i; the current required to drive the drain of Q1 is i, leaving hfe*i to drive the output.
(I've ignored the signal currents in the resistors, they are not relevant to the basic operation of the circuit.)

Jim

[Radio Wrangler]

It looks like the circuit of a quite decent active probe, and that low capacitance is valuable in not de-tuning the circuit being probed. I have a few of the HP 500MHz active probes which use similar techniques.

The error in the analysis is seeing the drain as an output. As turretslug just wrote, the impedance out of the emitter follower output is far lower than the impedance at the drain, so the drain is being driven.


David

[mhennessy]

Yet another way to look at this would be to "Thévenise" the circuits either side of C2. By guestimating the source impedances of Q1 drain and Q2 emitter, you can see in an instant that the latter wins. I know this is just a slightly different way of stating what has already been said, but Thévenin's theorem is something I use a lot, and find it very intuitive...

I'm not sure that this circuit can be called a compound follower though. There is no negative feedback around it - there are two positive feedback paths for bootstrapping, of course, but I see a source follower followed by an emitter follower. My understanding of a compound pair is shown on the left of the first diagram on this page: http://sound.westhost.com/articles/cmpd-vs-darl.htm - note the 100% negative feedback between the two devices.

So, is my understanding of the nomenclature wrong, or can two isolated (at LF, at least) followers be described as "compound"? Just curious...

[Skywave]

Originally Posted by turretslug

The signal from Q2 emitter is at much lower impedance than that from Q1 drain, so it will dominate and take Q1 drain along with it.

O.K., that I now understand - thank you. I've never met this technique before, which is why I was puzzled. In retrospect and with that understanding, it seems quite a clever technique.

Al.

[G8HQP Dave]

One follower after another follower is a cascaded follower, not a compound follower.

I always thought that the impedances of a split i.e. equal source/cathode, drain/anode resistance stage was the same because of local negative feedback. Within 1/gain anyway.

[mhennessy]

Do you mean configurations where you have an active device - let's call it a bipolar transistor for ease - that has equal resistors connected to the emitter and collector? The sort of thing that is used as a phase splitter? What Q2 above looks like if you strip away everything else, leaving just the 10k resistors?

If so, the output impedance of the signal taken from the collector is equal to the collector resistance. Well, near enough - the transistor itself will affect it slightly, but for the purposes of understanding, you can ignore that.

Meanwhile, the output impedance of the signal taken from the emitter is very much lower. This is an emitter-follower, so you've got re (which is 1/gm), and whatever the source impedance of the preceding stage is, but divided by Hfe.

Of course, the device is reacting to the voltage difference between base and emitter (or gate and source, or grid and cathode) => the local negative feedback you mention...

[kalee20]

No,they are quite different.

Load the anode/drain, and the voltage drops appreciably.

Load the cathode/source, and the voltage drops only a bit, and the anode/drain voltage rises!

If you give the cathode and the anode equal loads, the voltages will be equal whatever.

Skywave's initial query is for a simple but interesting circuit. Nothing much further to add to what has been posted already - yes, it's a cascaded follower bootstrapped back to the first stage drain. It'll give a really low input capacitance as the first-stage FET has all 3 pins seeing almost the same signal, in amplitude and phase.

[Skywave]

My questions about this circuit have now been answered: my thanks to everyone who contributed to this thread.

However, it is threads like this that illustrate just how useful a facility this Forum is. Many years ago (pre-Internet era), the chances of getting a question (such as this one) answered were minimal - if at all - and the resultant ignorance would thus remain.
But to get back on topic: my question has been answered; no further comments from me are necessary, but I'm sure others will wish to add further useful comments to this thread. Those I will read - and learn from them.

Al. / Nov. 3, '14 //

[Skywave]

Originally Posted by Skywave

My question has been answered; no further comments from me are necessary.

What was that about tempting fate?

The source of this cct. is Linear Applications, 2nd. ed., by National Semiconductor (dates from 1980, approx.) The cct. appears on page AN32-1.
The BJT is shown as an NPN and the type number '2N3644' is ascribed to it. However, I looked up the spec. for that transistor in various sources - and it seems that a 2N3644 is a PNP! Whoops!
Perhaps a 2N3664 was intended.

Al.

[G0HZU_JMR]

One thing to note is that the gate is biased at a third of the supply rail. Therefore, with the other bias resistors in the source and drain the circuit would need to be run at quite a high supply voltage in order to get the JFET out of its linear region and into the saturation region for correct operation.

eg a >= 24V supply may be required to get the JFET reliably into the saturation region. If you ran it at a voltage much lower than this I don't think it would deliver the expected performance in terms of ultra Hi Z at the input.

You could try increasing the value of the 2M2 resistor (R1) if you wanted to run it at a lower supply voltage. That might work OK...