FOTH RGB combiner problems

[jim_beacon]

Various people remarked on the noisy and wide line synch pulse displayed on the Tek 529 waveform monitor when I demonstrated the FOTH standards converter at Harpenden last weekend.

A little investigation has shown that this is due to the XOR synch combiner, the synch pulse is stretched by the cpacitance in the combiner circuit (this is used to allow positive or negative going synch pulses without altering the circuit), and the noise seen in the bottom of the "stretched" pulse is coincident with the end of the input pulse - I suspect this is due to poor screening and excessive cpacitance in my construction (I'll admit it Jeffrey, I shouldn't have used stripboard).

I think the definitive cure is to remove the capacitance from the input of the synch combiner, and rely on the X-config modeline to set the synch polarity correctly. Altering the capacitor value would improve matters, but only for one particular standard. Of course the ideal solution would be to completley redesign the synch combiner to properly regenerate the synch for the relevant standard.

Jim.

[oldeurope]

Hm, not easy to understand without a schematic.
Darius

[Kat Manton]

Hi,

This should help: http://www.technogoths.demon.co.uk/405/RGB-conv-II.png

I've also noticed noisy,stretched sync pulses; I've yet to investigate (too many things to do, on top of which I've caught 'flu or something.)

The capacitors to which Jim refers are C1 and C2 - which are both part of RC filters with ridiculously long time-constant (compared to the pulses being fed in), which essentially remove all traces of sync pulse from one input of the XOR gate. So, one input of the gate is held steady (steady in logic terms), the other is pulsed. The result is that whatever polarity pulse you feed in, you get positive-going pulses coming out.

As far as I remember from 'scoping that part of the circuit while I was building it; the sync pulses emerging from IC1 pins 3 and 6 weren't stretched - if they were I'd have dropped automatic sync polarity detection.

When I was working on it leading up to NVCF, I remember everything being fine coming out of the last XOR gate, but it all went wrong in the subsequent transistor stages; that's where the pulse stretching occurred. I didn't look into it as I was running out of time and I've not had chance since to investigate either (mostly as I regard this sync combiner as a filthy hack and want to design something with a PLL run at twice line rate which regenerates proper syncs). I suspect lousy design on my part; I should stick to digital stuff and microprocessors

Regards, Kat

[oldeurope]

Hi Kat,
thanks for your schematic.
Your problem is two transistors Q8 and Q11 are going to saturation.
This makes the pulses longer.
Are you sure with D1 and Q6 ?
I don't know the voltage of the black level, but it seems possible
to feed the sync from pin8 via a resistor to emitter of Q7.
In this case you don't need R23 R28 R29 Q8 Q11 and R17 is 100 Ohms.
(higher bandwidth!)
For serration pulses a solution with fH x 10 and a modulo counter is
independent from the standart. But the fH x 2 and monostables works fine
too.

Kind regards
Darius

Reason for editing: I didn't see the minus 5V, I thaught it is ground
this negative voltage rail makes it complicated . Speedup your transistors Q8 and Q11
with a schottky speedup Diode BAT46.

[Kat Manton]

Hi Darius,

Originally Posted by Darius

Your problem is two transistors Q8 and Q11 are going to saturation. This makes the pulses longer.

I wondered if saturation of one or both transistors might be the problem. I've been thinking about using a FET or two in this area instead, I don't like bipolars much. To be honest, I don't like discrete-component solid-state circuitry much, either. Give me op-amps and nice complex IC's, please

Are you sure with D1 and Q6 ?

D1 is there to allow me to set either sync tips at 0V or black level at 0V by adjusting R20. Odd idea I've never seen used anywhere else before, but it seemed to work so I left it.

You've spotted (yet another) mistake on the schematic, both outputs are of course identical circuits; all sorts of errors crept in transferring the drawings from scraps of paper to the computer. I've amended that bit, it now matches what's on my veroboard.

I didn't see the minus 5V, I thaught it is ground
this negative voltage rail makes it complicated.

It does, but I wanted to be able to have black level at 0V and negative-going sync.

At the point where sync is inserted, the video signal (on the right-hand end of R17) is somewhere below the 0V rail; hence the need for Q8 as a level-shifter.

To be honest, I'm probably not going to bother refining this circuit any further myself; it was really another lashup that just happened to be better than the last lashup.

Video op-amps are the way forward; component count comes down, performance improves and designing the thing gets a whole lot easier. Jim Beacon's working on a circuit using a video op-amp; I'm likely to take the analogue parts of that but replace the XOR sync combiner with something else; lots of nice digital stuff...

Regards, Kat

[oldeurope]

"Give me op-amps and nice complex IC's, please"

Replace Q8 Q11 by an TTL to RS232 IC

"D1 is there to allow me to set either sync tips at 0V or black level at 0V by adjusting R20. Odd idea I've never seen used anywhere else before, but it seemed to work so I left it."

Sorry I didn't see the -5V rail. With +-5V it makes sense to me.

Kind regards
Darius

[Kat Manton]

Hi,

Originally Posted by Darius

Replace Q8 Q11 by an TTL to RS232 IC

Now there's an idea. I've got several flavours of RS232 line-driver in my junk box. Nice fast level shifter...

Cheers, Kat

[jim_beacon]

Darius,

you are, of course, right, scoping the unit shows the worst of the stretching occurs on the sync clamp. I may have been a little premature with my other comments.

I hope my new op-amp combiner will cure the problem, but as I currently have Sony 9-90 problems, so development has halted for a few days.

Jim.

[Kat Manton]

Hi,

If you think that C1 and C2 are still a problem, just make them bigger - all that'll happen is the circuit will take longer to stabilise. As long as the signal on the +ve end of each capacitor never rises above (or falls below, depending on sync polarity) the logic threshold all will be well - i.e., the logic level as seen by pins 2 and 5 of the gate should not change at all once the circuit has stabilised. The values were calculated as conservative for 405-line, so will be ok for 625, 819, etc; but C1 and C2 may need increasing if you use it on slower standards such as 240-line - depends how conservative I was, they might be ok

Regards, Kat

[Kat Manton]

Hi again...

...just a thought, a workaround for the sync-pulse stretching of this combiner could be to reduce the width of the sync pulse as it comes from the computer. Reduce the third number (sync pulse end) in the horizontal section of the modeline (as long as it remains a multiple of eight) to make up for the stretching...

I'm probably going to do something similar with the modeline for the proper SPG circuit; I'll probably set the front porch to zero and the sync pulse quite short, the SPG circuitry locked to this can then generate sync with the correct front porch length and sync pulse length, more accurately than can be set by modeline alone (that pesky "multiple of eight" thing gets in the way.)

Regards, Kat

[oldeurope]

Hi Kat, you should use a schmitt after the C1 and C2. The LS86 wants
TTL level.
I am not sure understanding your power supply. The -5V is not stabilized?
(+5V -6V3)

"Video op-amps are the way forward; component count comes down, performance improves and designing the thing gets a whole lot easier"

I don't agree. And I want the sync tips on 0V !


"Now there's an idea. I've got several flavours of RS232 line-driver in my junk box."
Do you have some MC145406 in a small smd package?
I got some from RS order code 273-270 and they are big smd's.

Kind regards
Darius

[jim_beacon]

Originally Posted by Darius

I am not sure understanding your power supply. The -5V is not stabilized?
(+5V -6V3)

The power supply is designed to run from a single rail stabilised supply.

Originally Posted by Darius

"Video op-amps are the way forward; component count comes down, performance improves and designing the thing gets a whole lot easier"

I don't agree. And I want the sync tips on 0V !

In my new design, I can put the sync tips wherever I like (within reason) by a simple trimmer, I can also vary the proportion of sync and video, as required by some other standards. Using video op-amps made this flexibility very easy to achieve.

Unfortunatly, this is on hold at the moment.

Jim.

[Kat Manton]

Originally Posted by Darius

Hi Kat, you should use a schmitt after the C1 and C2. The LS86 wants
TTL level.

Not necessary in my opinion; the sync pulses from the computer are TTL-level already; and the filter time constant should be long enough for the levels after the RC filter to never drop below (or rise above) the respective logic threshold anyway once the charge on the capacitors has stabilised.

I am not sure understanding your power supply. The -5V is not stabilized?
(+5V -6V3)

The -5V rail isn't really -5V, it's whatever's left over after 5V (and a diode drop) has been subtracted from the regulated supply you run it off. (I'm lazy and used the "-5V" library part - only true if you run off 10.6V...) I'm running off a regulated 12V wall-wart, so the -ve rail regulation is as good as the regulation of the wall-wart - good enough with the linear regulated one I'm using.

"Video op-amps are the way forward; component count comes down, performance improves and designing the thing gets a whole lot easier"

I don't agree. And I want the sync tips on 0V !

I can get sync tips at 0V if you like; it just takes a tweak of R20 while watching the output on a 'scope...

For what it's worth, my opinion is that any circuit which needs a video signal referenced or clamped such that some part of it is at a fixed level, then it should be the responsibility of that circuit to do it.

The standard for video signals appears to merely specify 1V p-p and 0.3V sync but not that anything is referenced to anything. If I needed sync tips at zero for anything following this (modulator, probably) I'd AC-couple the input and clamp sync tips to 0V myself; thus making the input compatible with anything I feed into it. I have no idea what my VCR produces, for example.

Personally I want black level at 0V as I might end up with several sources of 405-line video at this rate, black=0V makes switching (or even fading if everything's synced together...) nicer.

"Now there's an idea. I've got several flavours of RS232 line-driver in my junk box."
Do you have some MC145406 in a small smd package?
I got some from RS order code 273-270 and they are big smd's.

Sorry, no SMD parts here at all; mostly I've got "classic" MC1488/MC1489 and some Maxim parts; all standard 0.1" DIL package.

Regards, Kat

[oldeurope]

Hi Jim, all you want can be made discrete or with opamps.
If you know transistors, some parts can be designed much easyer.
This is why my analogue converter uses much of them.
There was one stage I was thinking of an opamp use. But it gave
no advantage.

Kat, please beleve me, a 2K2 is not a save pull down for TTL inputs!

Kind regards
Darius

[oldeurope]

...And change R34 R37 in 100 Ohms !!!
The best is to use a 74LS244 input buffer. (Schmitt!)

Darius

[Station X]

I've got some MAX232 TTL to RS232 DIL convertor chips here which I doubt I'll ever use. FOC to anyone who wants to experiment.

[Kat Manton]

Hi,

I think I need to explain more how IC1A and IC1B and the long time-constant RC filters (R35/C1 and R38/C2) work together with the XOR gates to invert negative-going sync but cunningly not invert positive-going sync; such that whatever polarity sync you feed in from the computer, you always get positive-going sync at the output of IC1A and IC1B. I know how it works; and it does work, but I seem to be failing to explain it. Maybe I need to draw some waveform diagrams, or even photograph them off the 'scope?

Anyway, the H and V sync output of the graphics card is already clean, sharp and TTL-level, with nice fast rise and fall times, so my opinion is that there is no need for a Schmitt anything anywhere to clean up that which is already clean.

The inputs to IC1A and IC1B after the RC filters (R35/C1 and R38/C2), on pins 2 and 5 respectively, are at as near as dammit a steady level some (short) time after the computer has been fired up. To further clarify:

• If the sync input is positive-going, the voltage after the filter (on pin 2 or 5) is always below the threshold for logic zero. Fixed logic 0 on one input, pulses of logic 1 on the other, output of gate is positive-going sync pulses.
• If the sync input is negative-going, the voltage after the filter (on pin 2 or 5) is always above the threshold for logic one. Fixed logic 1 on one input, pulses of logic 0 on the other, output of gate is again positive-going sync pulses.

So, no Schmitt input anything is needed here either as, during normal operation, the voltages on pins 2 and 5 of the XOR gates do not appreciably change nor go anywhere near any logic threshold level. If they do, then C1 and C2 aren't big enough to filter the sync pulses out.

If the sync polarity changes, there may be some spurious transitions as the voltages on pins 2 and 5 take up their new steady levels, but once the system's running the sync polarity doesn't change so there isn't a problem.

Regards, Kat

[oldeurope]

Kat, thanks for explaining, but I know this stages from monitors.
The 74LS244 or 240 is the best.
I made a lot of VGA switches and splitters and I know what I am talking
about.
Digital inputs driven over a cable from
another source need a buffer at the input.
With your values for R34 35 37 38 you can try a 74HC86 or better 4030 4070.
I am sure this solves your sync problems.

Kind regards
Darius

[Kat Manton]

Hi Darius,

Originally Posted by Darius

Kat, thanks for explaining, but I know this stages from monitors.

Fair enough.

The purpose of the Mk2 combiner was to be a better lash-up than the Mk1 lash-up; which had appalling DC level stability issues; black-level was all over the place and varied with scene content. The Mk2 circuit as produced works well enough; one requirement was to keep component count down and be able to build the thing in time for NVCF; something I only just managed; I was still soldering bits on veroboard at 8pm the night before, and was up at 4am to drive down...

I don't consider it a final design and I'm basically going to abandon it completely and work on something different and better.

I am sure this solves your sync problems.

The problems with this circuit are:

• Level-shifter transistors both operated as saturated switches, hence stretching the sync pulse. (Workaround - reduce sync pulse length in modeline as covered above.)
• Sync is XORed; so VBI is all wrong and produces line-pairing on my Pye monitor.
• Some DC level drift as the whole mess warms up.
• Overall component count too high for my liking. I prefer a few ICs to a lot of transistors.

New version (Mk3):

• Op-amp for RGB summing.
• Active clamp to set DC level wherever you want it (sync tips or black level at 0V at the flick of a switch) and deal with the DC drift problems.
• Either a PLL run at twice line-rate and some other digital electronics or maybe even a small microcontroller, synced to line-sync and generating proper sync for whatever standard the PC is producing.
• Probably all surface-mount and on a PCB as well.

This would likely have any buffering on the inputs necessary; run entirely off the 5V rail present on pin 9 of most graphics cards (generating a -ve rail internally, ICL7660 take a bow...) with an option to plug a wall-wart in on the offchance the card doesn't have 5V on pin 9.

A microcontroller of some sort is in the lead here as it gets the sync generation and timing under software control, where I like it. I can then detect what TV standard the PC is producing then generate correct syncs as required in software; which suits my way of working. It might also be worth my while looking at the smaller FPGAs as an alternative to a microcontroller.

Regards, Kat

[Sean Williams]

Originally Posted by Kat Manton

This would likely have any buffering on the inputs necessary; run entirely off the 5V rail present on pin 9 of most graphics cards (generating a -ve rail internally, ICL7660 take a bow...) with an option to plug a wall-wart in on the offchance the card doesn't have 5V on pin 9.

Hi Kat,

I have some problems with the ICL7660 - although a great device, it does get intolerably hot when asked to do any work - I have some commercial gear here that uses one to generate a bias supply for an amplifier stage - just waiting for the magic smoke......


Long live discretes and high component counts

Cheers
Sean