The great FET mystery

[Skywave]

Wendy: so you've had trouble with using PN4416 as amplifiers, too, eh? If you can recall your supplier, perhaps you'd like to tell me who in an e-mail. (I'm mindful of the Forum rules here).

Al.

[trh01uk]

Back in the 1970s, Pye Telecom (whom I worked for back then) used JFETs a lot in RF front-ends on typical VHF/UHF receivers. They would be good in a variety of roles, RF amps, mixers, etc.

As I recall, the bias resistors would always be "select on test". And that was because FETs at the time (e.g. J309) were notoriously variable in their static characteristics. "Select on test" is a fiddly, time consuming and expensive business on a production line. Its means you have to have a technician carry out tests, decide on the correct resistor and fit it - you can't use an unskilled person for the job - at least you couldn't back then - no doubt modern pick and place machines can "do it all".

So we shouldn't be surprised when the experience is that FETs can be somewhat "troublesome".

Richard

[Phil G4SPZ]

Yes, this wide spread of characteristics surprised me when I started testing FETs. The popular 2N3819's Vgs for 200uA drain current ranges from -0.5 to -7.5 volts, and the drain current at zero Vgs can be anything between 2 to 20mA!

I also discovered, through experimentation, that transconductance varies significantly depending on the drain current at which it is measured. Perhaps Al's examples weren't being biased correctly in circuit? It would be interesting to be able to measure the characteristics of one of the suspect devices.

[Wendymott]

Hi Al. They were removed from an old piece of equipment, my Adret signal generator. Kept em in case they came useful.
I bought some more from Ebay, as I am trying to replicate my Marconi RF Meter and they switch ok, but not tried these as amps.

[G8HQP Dave]

Originally Posted by Phil G4SPZ

I also discovered, through experimentation, that transconductance varies significantly depending on the drain current at which it is measured.

As JFETs are square-law devices, we should expect that transconductance varies linearly with current.

[Phil G4SPZ]

It's interesting that you should mention this, Dave, because I'm not quite sure how I should interpret the test results that I get from my DC FET tester compared with the data sheets. I hope this isn't drifting too far off topic, but the data sheets I've read quote forward transconductance (in microMhos) under small-signal AC conditions, with Vgs equal to zero. My tester measures gm and is calibrated in mA/V. Converting from uMho to mA/V is straightforward (divide by 1,000) and I can get results that fall within the quoted range, but it's highly dependent on the drain current.

Sadly, I have no instructions for the tester and have tried to work it out by trial and error, but it seems that reasonably consistent results for gm are obtained at around 1mA Ids. The tester does not test gm by applying a small change to Vgs, as a valve tester does. I conclude that as long as a reasonable amount of gain is demonstrated, then the device is a good 'un!

[G8HQP Dave]

Datasheets like to maximise figures-of-merit, without actually cheating. Hence transconductance is often quoted on the front page at maximum current (Vgs=0), while hidden away somewhere on page 5 there will be a small graph showing how it varies with current.

You can't measure gm without varying Vgs.

[Phil G4SPZ]

You're quite right... and I just measured again what happens to the applied Vgs when measuring gm on the tester. Vgs does indeed change - by a mere 6mV, and I had been looking for something much bigger - but the test does simulate a small signal.

[jimmc101]

I suspect that there may be nothing wrong with the FETs, in each circuit it is the biasing that is causing the problem.

I’ve run both circuits (as I understand them) through a simulator (Simetrix) and certainly the first circuit has problems.

The PN4416 in the simulator library has the following characteristics
IDSS 12.1mA, VGS0 3.53v and GFS0 6.6mA/V

In the first circuit the FET is saturated, the source is at 1.06v and the drain at 1.36v and the output less than3mV pk-pk.
Reducing the drain resistor to 3k3 brings the device out of saturation and gives a gain of to just over 7.
If the BF256A you used had a lower VGS0 it would not saturate.


I’m not so sure about the second circuit, the FET is run at a quite low drain current of about 110uA so the gm is quite low, approx. 600uA/V, giving an overall gain of about 3 to 5 depending on the hfe of the PNP.
The BF256A is a lower current device and will work a little better under these conditions.

Jim

[Skywave]

Originally Posted by jimmc101

I’ve run both circuits (as I understand them) through a simulator (Simetrix) and certainly the first circuit has problems.
In the first circuit the FET is saturated, the source is at 1.06v and the drain at 1.36v and the output less than3mV pk-pk.
Reducing the drain resistor to 3k3 brings the device out of saturation and gives a gain of to just over 7.

Thanks, Jim, for your valued input.

The simple test jig that I built - which you have simulated - was later modified: I replaced the 10 kΩ drain resistor with a 1kΩ resistor and a 10kΩ variable resistor. I tried measuring the gain as that variable R was changed - but the result was still low gain - if any. However, when a BF256A was substituted, yes, the gain did vary as that R was varied (as we would expect), and substantial voltage gains were then observed.

Al.

[kalee20]

Originally Posted by jimmc101

The PN4416 in the simulator library has the following characteristics
IDSS 12.1mA, VGS0 3.53v and GFS0 6.6mA/V

In the first circuit the FET is saturated, the source is at 1.06v and the drain at 1.36v and the output less than3mV pk-pk.
Reducing the drain resistor to 3k3 brings the device out of saturation and gives a gain of to just over 7.

Errr... There may be terminology confusion here!

If the source voltage is 1.06V and the drain 1.36V, then there's 0.3V across the FET - quite low - and it definitely isn't saturated, it'll be in the linear region (Id proportional to Vds assuming constant gate voltage).

Saturation in FETs refers to when the drain - source voltage is high, the drain current is then virtually independent of drain voltage, just like a valve that's saturated (anode current limited by cathode emission - not that we like operating our valves like this, of course!). The jFet's drain current will depend only on gate voltage.

Operating the FET under saturation conditions DOES result generally in the highest gain, unlike bipolar transistors (where 'saturation' refers to the base-collector junction being saturated with charge carriers, the total voltage drop very low, and gain virtually non-existent).

[jimmc101]

Thanks for the correction, I confess that in private I misuse the term 'Saturated' for FETs and forgot to correct myself.
I not sure what to use, 'ohmic region' is not specific enough; I suppose 'bottomed' would mean the same for both FETs and BJTs.

I can only assume that physicists must have defined the term, it makes no sense to me to call opposite ends of the (relatively) similar output curves of FETs and BJTs by the same name.

Jim