Non-working Commodore PET 3016

[ScottishColin]

It didn't come in today's post. Hopefully tomorrow.

Colin.

Originally Posted by SiriusHardware

By the time we get to the far corner I'm expecting... jellyfish.

If UH1 arrives today, can you redo the checks for activity on the two Q outputs of UH1, if there is some, look for activity on the output of the 74LS08 gate that those pins are connected to the inputs of.

[SiriusHardware]

Well, at least that gives me time to be more specific:-

Fit new UH1 (when it arrives). Leave the NOP tester fitted.

Check for activity on:-

UH1 pin 6 and UG1 pin 13 (should be the same signal)

UH1 pin 8 and UG1 pin 12 (should be the same signal)

If you have activity on pins 12, 13 of UG1 but no activity on UG1 pin 11, replace UG1.

-If you do have activity on UG1 pin 11, fit the CPU directly and see what happens now.

[ScottishColin]

I'm wondering if you could help me with the schematics?

I see UH1 on page 6 - I'm wondering why pins 5 and 9 are shown but they seem to go nowhere? Or am I missing something?

Colin.

[ajgriff]

Unused outputs presumably. Are they connected to anything on the board itself?

Alan

[SiriusHardware]

pins 5 and 9 are shown but they seem to go nowhere

They are shown, and they are shown to go nowhere just as you say. It's quite common for all of the pins on an IC, even the ones which are not used, to be shown on the circuit diagram - mainly to remove any doubt over the question: Are those pins used in this circuit or not? Each of the two elements inside the UH1 IC has two outputs, a 'Q' output and a 'Q' output, but in this case only the 'Q' outputs are used.

There is also another, potentially much more confusing convention used on this diagram (and many others). Look at UH1 and tell me which of its pins are the +5V and 0V supply pins for the chip? You can't find them? Not on the diagram, no, because it is also normal for the power supply pins - and the wires that would be going to them - not to be shown on digital circuits, or at least not the supplies to, and the supply pins of, the standard logic ICs.

The reason is that on digital logic ICs the power supply pins are nearly always +V to the upper right corner pin - the highest numbered pin on the chip, and the 0V supply pin is nearly always the lower left corner pin, so leaving out the power supply pins and the wiring to them removes a lot of 'unnecessary' wiring spaghetti from the circuit diagram. If you ever have any doubt as to where the supply pins are on an IC the best way to be sure is to google for the pinout for that IC, as the datasheet will always tell you where the power pins on the IC are.

This convention does not really apply to 'Big' ICs. Although a fair number of those also have their supply pins on the upper rightmost and lower leftmost pins, a great many (including your 6502) do not, so for ICs like that the supply connections to the IC are always explicitly shown as they can't be assumed to be on opposite diagonal corners of the IC.

[ScottishColin]

Nope. I wonder why they are identified though?

Pins 7 and 14 are not shown - I suppose that's a convention though?

Also on the same page, why is G1 (and 7, 10 and H10) a different shape to the other ICs?

Colin.

Originally Posted by ajgriff

Unused outputs presumably. Are they connected to anything on the board itself?

Alan

[ajgriff]

Originally Posted by ScottishColin

Also on the same page, why is G1 (and 7, 10 and H10) a different shape to the other ICs?

Another so called convention. Just a way of illustrating NAND gates. This Wiki entry illustrates some of the symbols used in TTL circuits:

https://en.wikipedia.org/wiki/Logic_gate

Alan

[SiriusHardware]

The different shapes of basic gates usually signify the type of logic gate they are.

A brief search found this page which explains the differences and the different symbols used to represent them.

https://www.elprocus.com/basic-logic...-truth-tables/

However, Commodore have gone one step further here and modified some of the chip gate symbols to reflect the way they are used. UG1 is a 74LS08 and the 74LS08 contains 4 separate AND gates, which are usually represented as a bullet-shaped element with a 'straight' back end. We can see three of the elements of UG1 on sheet 6, but the one to the right of UH1 is not drawn as an AND gate. Instead it is drawn as an OR gate with little inversion circles on all its pins. This is Commodore trying to indicate that this gate is being used as an 'inverse OR' gate - when one input OR the other input is low (or both inputs are low), the output is low.

Crossed with aj.

[ScottishColin]

Thank you both. That's all very helpful.

Colin.

Originally Posted by SiriusHardware

The different shapes of basic gates usually signify the type of logic gate they are.

A brief search found this page which explains the differences and the different symbols used to represent them.

https://www.elprocus.com/basic-logic...-truth-tables/

However, Commodore have gone one step further here and modified some of the chip gate symbols to reflect the way they are used. UG1 is a 74LS08 and the 74LS08 contains 4 separate AND gates, which are usually represented as a bullet-shaped element with a 'straight' back end. We can see three of the elements of UG1 on sheet 6, but the one to the right of UH1 is not drawn as an AND gate. Instead it is drawn as an OR gate with little inversion circles on all its pins. This is Commodore trying to indicate that this gate is being used as an 'inverse OR' gate - when one input OR the other input is low (or both inputs are low), the output is low.

Crossed with aj.

[Mark1960]

The PET schematics are quite nicely drawn compared to those for the MK14. They show both the pin numbers and the function of each pin. I really like the way they show the gates, it helps readability a lot when AND gates used as inverted OR gates are drawn that way. I’m just a little bit too lazy to do that in my own schematics.

Some of my pet hates in schematics are where logic gate ICs are drawn as a block in the pin layout of the IC, or where someone draws a single bus and everything connects to named connections on the bus.

[julie_m]

I do like the way they have drawn some NOR gates as ANDs with NOT circles on the inputs, and NANDs and ORs with NOT circles on the inputs. It makes it obvious whether they were looking for any of the inputs to be in a certain state, or all of them at once.

After all, the whole point of a diagram is to impart information; so anything that gives you a clearer idea what is supposed to be happening is a good thing.

[SiriusHardware]

OK for us, I guess, but slightly unhelpful for Colin for whom I would imagine this is the most complex circuit diagram he has ever attempted to read - so customised logic symbols probably aren't too welcome at this stage.

[ortek_service]

I suppose that with modern CAD PCB Systems, with schematics tied to PCB via parts libraries then doing the odd gate differently is a bit more awkward, having to build a custom part for it. So it was easier to do when schematics were mostly hand-drawn (Although less chance of errors on schematics, when they are closely-link to PCB layout via netlist).

I have recently found that some IC manufacturers like TI / distributors like Mouser with auto creation of symbols for your CAD system can just give you the rectangle pin-out view of the part. Although TI also sometimes use them on their own eval board schematics, rather than making them a bit more 'logical' with power pins top & bottom at least.

Yes, I have encountered those single bus / harness schematics with everything on it (rather than having separate data/address buses / labelled-function harnesses for specific mixed-signals between blocks). I suppose if it's on a CAD system / generated PDF, then you can at least use Ctrl-F to find all instances of a connection. But a bit more of a pain when printed.


By using power rail-bar & ground symbols, connected directly onto labelled pins of the first logic gate on a multi-gate package, then it's not too much extra to include. And can always put all the decoupling in parallel in another area - where it was often common to put arrows to the supplies to each IC/ can have an extra power-rails block in the CAD part these days for each IC.

I'm not a fan of hidden power rail connections, as then not on printed schematics (I saw this recently on an Eagle? one, but in the past had only known it being used on v.expensive Mentor system where we found due to an error somewhere, a failed IC never had power to it and was just getting parasitically-powered via its inputs).

[Mark1960]

Originally Posted by ortek_service

I'm not a fan of hidden power rail connections, as then not on printed schematics (I saw this recently on an Eagle? one, but in the past had only known it being used on v.expensive Mentor system where we found due to an error somewhere, a failed IC never had power to it and was just getting parasitically-powered via its inputs).

Yes eagle will add default power connections if the parts are designed like that, but if you use the electrical rules check it will give warnings. This is when the pin for the part is designated Vcc and you have the net named Vcc in the design. If your net is named +5v then it won’t connect power to the component.

[Mark1960]

A couple of the things I noticed in the pet schematic that I don’t like is where they tie unused inputs directly to 5v, but maybe thats just me starting with 74 series TTL. Design rule was always use a pull up resistor to 5v, but OK to tie to 0v. Even worse is that the inputs to an unused multiplexer in the dynamic ram circuit are left floating, I guess we’ll soon find out if that really does reduce the life of the component.

[ortek_service]

Although not too good practice, I seem to recall that 74LS TTL inputs floated high, due to input circuitry (and at least had high-level threshold down at 2V).

Whereas CMOS inputs, definitely shouldn't be left floating as couldn't guarantee any state with 1/3 & 2/3 x Vcc L / H thresholds. And also a bad idea on unused gates, as supply current higher when both N & P MOSFET's are partially on together with it mainly only limited by their Rds(On)'s - Which was quite high on 4000-series, making them quite slow but low-power, but with much lower resistance FET's in 74AHC etc, supply current could go upto 100's of mA's if inputs left floating

[SiriusHardware]

I'm guessing that 74S74 still hasn't flopped onto Colin's doormat. Let's hope that when it does, it will prove to have been worth waiting for.

[ScottishColin]

You can be sure I'll let you know when it turns up - I need all the help I can get.

Colin.

[ScottishColin]

Good evening ladies & gentlemen - back to business at last.

New UH1 fitted.

UH1/6 and UG1/13 - same signals

UH1/8 and UG1/12 - same signals

Activity on UG1/11, 12 and 13.

Plugged CPU in directly and I'm back to my blank screen (with power to the monitor as I can turn the contrast up and see the green lines).

Colin.

Originally Posted by SiriusHardware

Well, at least that gives me time to be more specific:-

Fit new UH1 (when it arrives). Leave the NOP tester fitted.

Check for activity on:-

UH1 pin 6 and UG1 pin 13 (should be the same signal)

UH1 pin 8 and UG1 pin 12 (should be the same signal)

If you have activity on pins 12, 13 of UG1 but no activity on UG1 pin 11, replace UG1.

-If you do have activity on UG1 pin 11, fit the CPU directly and see what happens now.

[SiriusHardware]

Welcome back. Good to know that the wait wasn't a waste of time since those signals are getting a bit further now and, as predicted, it looks as though UG1 decided it would be pointless to be faulty because you had a replacement UG1 ready and waiting. It is however still possible for one of the other three elements of UG1 to be faulty, so don't lose that spare IC.

The CPU obviously still is not returning from the initial ROM subroutine call in which it (successfully) clears the screen, so that still points to a possible system RAM fault preventing correct operation of the stack - if not the RAM itself, then one or more of the remaining RAM system support ICs.

We'll have a think about this - we're probably going to have to go back to the NOP test again and follow these signals a bit further. It is getting closer to the point where we are going to have to try to run some test code (I have that in hand, adaptor is made, I just have to programme a couple of EPROMs or EEPROMs with the test code).