Franklin VFO ?

[G6Tanuki]

Originally Posted by G0HZU_JMR

One niggle with this circuit is that it isn't immediately obvious how to (efficiently) tap off energy from it with a buffer amplifier. This is because of the very large voltage waveforms and the high impedances involved.

What about a 'secondary' winding of a couple of turns around the main inductor, feeding into a Class-A-biased emitter- or source-follower? That gets away from the issue of hooking loads up to high-impedance points associated directly with the electrodes of the active devices.

Another thing to ponder: I've never really liked valve or FET oscillators where they basically run at high-gain and depend on self-generated grid/gate-bias and grid/gate resistors to limit the oscillation amplitude. One of my most-successful oscillators was a simple Colpitts JFET (BF256) from a design in ART - with the gate DC-grounded (through the coil) and a resistor in the source-ground lead to set the static bias. With deliberately-low feedback, the DC conditions didn't change whether it was oscillating or not.

[Bazz4CQJ]

Hopefully, without taking the thread off topic, can anyone point me at a good source of information about the design of analogue (and maybe digital) RF oscillators? Thinking back to the days when PW, SWM and RadCom were primary sources of information for radio hams, they would clearly identify the need for frequency stability, and discuss how that was achieved, but I don't recall there being very many references to any other parameters. This thread has focussed on the issue of noise, and this and possibly other parameters presumably relate to a better level of understanding than was commonly around in the past? Please keep this at the "ham radio" level complexity .

B

[G0HZU_JMR]

What about a 'secondary' winding of a couple of turns around the main inductor, feeding into a Class-A-biased emitter- or source-follower? That gets away from the issue of hooking loads up to high-impedance points associated directly with the electrodes of the active devices.

Yes, that would be one way as long as the coupling was fairly light. It would also have the benefit of having low harmonics as the resonator waveform should be a fairly good sine wave.

By contrast, I think the second JFET in that oscillator could be running like a switch between Idss and pinch off so it will generate a comb of harmonics at the drain. The other issue is that the Idss will vary from device to device and the JFETS are biased to start up at Idss. I tried simulating the circuit in Microwave Office at work today and it was very fussy with respect to the choice of JFET model even if they were all from the P50 process group. So I think the small signal gain in the startup condition won't be that well defined from device to device. However, I got a very similar phase noise plot to the one I posted up earlier. The JFET model in MWO doesn't seem to account for flicker noise but apart from that the phase noise seemed very similar to my earlier guesstimate.

[G0HZU_JMR]

Hopefully, without taking the thread off topic, can anyone point me at a good source of information about the design of analogue (and maybe digital) RF oscillators?

I've yet to see a really good/balanced book on this subject. Many are heavy on equations yet very light on practical designs with real components and circuits and test results. I don't think it's a subject that lends itself to print very well so I can sympathise with the authors a bit. There seems to be a huge gulf between 'academic' publications on this subject (that have lots of dry text and far too many equations) and ham cookbook publications that do little to describe the design process or the performance of the oscillator.

In my early days I did learn quite a bit from the oscillator section in Hayward (Introduction to RF Design). This is a classic book but I think it is a bit dated now and it lacks any detail of real/practical oscillator designs and there isn't any modern simulation work to back up the theory. However, there are lots of useful nuggets of info in the oscillator section and a few classic (and simple) design equations. So I do recommend it as part of the learning curve. However, I don't think this book is enough on its own. Many will be disappointed by it in this respect and the presentation methods used in the book aren't for everyone. So it might not be a good choice as an introduction despite the title! The genuine value it offers might be best realised once having read a few other articles on oscillator design.

In my opinion, the best way to learn this stuff is with an RF simulator alongside. Sadly, Hayward has nothing in it that helps in this respect. An example of a book that is the extreme opposite is "Oscillator Design and Computer Simulation" by Randy Rhea. This is an old book from the dark days of MSDOS but chapter 2 does explain the classic simulation methods used for oscillator design and there are plenty of simulation examples with plots and circuits. But few of them are 'real' circuits you can build yourself. It is heavily based on RF simulation and this is no surprise as Rhea is the founder of Eagleware. I've been an Eagleware user for about 30 years now and this RF design software is an old friend

I may be wrong but I think this book is now available free online in electronic format. For a while it was bundled free with the software in pdf format. But it is based on the old MSDOS software so is very dated in terms of the screenshots of the simulations etc.

Hint: Start reading at Chapter 2 first! The time to read chapter 1 is after you have tried (and failed) to model and simulate your first oscillator, especially if you started up at VHF or UHF.


There are a few freebie RF simulators available these days that will be easily good enough for basic oscillator design. Eg RFSIM99 or QUCS or Simetrix(SPICE).

[G0HZU_JMR]

The major unknown would be the noise level. Since the oscillator is running at low level, would'nt this imply a highish close-in noise spectrum ?

This was probably the main question in the thread so maybe it's best to focus on this rather than get into specific oscillator types.

By close in phase noise I'm assuming you mean phase noise offsets in the range 100Hz to 50kHz. A voltage level of 224mV rms into 50R is about 1mW or 0dBm. This is quite a healthy signal level for a local oscillator. A typical level for a diode ring mixer might be +7dBm so this isn't much higher in level. So I don't think there will be any issues at all with close in phase noise.

You can get some idea of the power in the resonator of an oscillator by looking at the Vpkpk in the resonator and doing a few sums based on the loaded Q of the tank, the frequency and the capacitance (or inductance) in the tank. For example, At 11MHz with a loaded Q of 50 and a resonator capacitance of 100pF and about 10Vpkpk in the resonator the power would be a couple of mW or so.

If the noise figure of the active device (including resonator loss and non linearity effects) totalled 8dB and you chose a BJT oscillator there is enough info there to predict the close in phase noise fairly well. I find that the corner frequency for the flicker noise for a BJT is usually around 5kHz at these frequencies. Armed with the above info, there is enough there to do a crude prediction of phase noise using Leeson's equation.

The result is as the plot below. This is for a BJT. If a JFET is used I think the flicker corner frequency will be different. It could be 10-15kHz. Some FET types have really high flicker corner frequency. However, if 15kHz is entered then the phase noise doesn't degrade that much with the JFET. It only degrades the close in phase noise a couple of dB or so. So I haven't bothered to post up the JFET version of the plot below as it will be very close to this.

So as long as you end up with a decent loaded Q of >40 and something in the ballpark of 10Vpkpk in the resonator of your JFET based 11MHz Franklin oscillator (assuming a resonator capacitance in the ballpark of 70-100pF) you can't really go wrong with the close in phase noise of a free running VFO like this as long as there isn't a gross error in the overall design somewhere.

Where you might hit problems with the VE3RF circuit is in the spread in Idss for your chosen JFET. I think this will affect the starting gain quite a bit because it only takes a small change in Idss (away from maybe 4mA) to radically change the DC voltage at the drain of each JFET at startup. If this voltage gets quite low (idss approaching 6mA?) then I think the startup gain will begin to collapse. So this circuit is probably OK if you don't mind selecting a JFET with a sensible Idss figure that suits this circuit.

The other issue is how you extract energy from the oscillator without spoiling the loaded Q and without degrading the ultimate noise floor of your system. Get it wrong and you could end up with a far out noise floor plateau of -145dBc/Hz out to several hundred kHz. This will happen if you degrade the signal level too much with respect to thermal noise at -174dBm/Hz. Even if you then try and amplify it back up again, the damage is done and the noise plateau will remain!

However, the close in phase noise wouldn't be affected unless the buffer was somehow able to load the oscillator resonator or affect the overall loop response quite badly.

[Radio Wrangler]

Oscillators don't need high gain from their active devices in general, and can be made up to fairly close to the device's Ft.

Consequently good, low phase noise RF oscillators can be made with low noise audio transistors, chosen for their low flicker corner frequency.

There is a viewpoint which says that the output of an oscillator has no real carrier at all, that the appearance of one is simply an illusion of looking at the output with finite resolution bandwidth. Look with narrower and narrower bandwidths and you see the noise go higher and closer in... extrapolate and it's noise all the way to the top.

You can never make a real sinewave in an oscillator, you can only make filtered noise. If you do a good job the noise is so tightly filtered that the output looks so like a sinewave that you can use it as one for the purpose you had in mind.

The first time you meet this concept, it sort of knocks the foundations out from all you thought you knew. You then have to learn to live with it and eventually exploit it.

David

[G0HZU_JMR]

In this case I think the loop gain will collapse if the JFET Idss gets to 6mA or so. I think the MPF102 is a classic process 50 JFET but the datasheet implies a huge range in Idss is possible from 2mA to 20mA. So the builder of this circuit could be disappointed if the Idss of their batch of MPF102 JFETs was fairly high.

The 2N5484,5,6 series are also process 50 (from memory) and these JFETs are graded across this Idss range so a 2N5484 should have an Idss within 1 to 5mA according to the datasheet.

I think it would be fairly fatal to select the 2N5486 with its Idss range of 8-20mA as the Vds of the JFETs would collapse to little over 1V (because of the 1k ohm resistor in the drain) and I think the loop gain would collapse way below unity. So I think the oscillator wouldn't start up. The 2N5485 would be marginal but it might work OK. The 2N5484 would be the lowest risk assuming the Idss was somewhere around 2-4mA.

[Radio Wrangler]

That's a general problem with JFETs the Vp and Idss values have very large variation from individual to individual. Some degree of selection is needed for circuits to stand any chance.

The problem gets worst with published construction articles and kits. These are often built by relative newcomers and kits only have one off of each part. When a project fails to work, many constructors blame themselves and get discouraged.

In a production environment, we can't afford misfires and having to perform selection. Besides it's likely all the parts in stock are from the same batch and you might swap one part for a similar one. Fet based oscillators are popular in amateur radio circles, but they are noticeably less common in commercial equipment.

Mosfets in amplifiers tend to need bias adjustments, so they tend to be reserved for stages where they give compensating advantages. You can't afford to have to make an adjustment to every single stage.

There was a family of dual gate MOSFETS made with integrated, matched current mirrors to allow operation on low supplies (BF904 etc) These could be made to self-adjust but the manufacturers are steadily obsoleting them now phone chipsets have taken onboard more functions.

David

[G0HZU_JMR]

Yes, I often feel like the bad guy when I give a negative opinion on some of the magazine based projects posted on here The designs often don't take into account the spread in device characteristics etc. This must lead to a lot of confusion and frustration for any unlucky builders who try and emulate the original circuit using parts that are slightly different in terms of tolerance etc.

I managed to find and grab some (SMD) 2N5484,5,6 JFETS at work and for a bit of fun I've tacked together a copy of the original VE3RF 5.5MHz oscillator onto some bare PCB. I've had to use some sticky pads to mount the SMD JFETs and so far I've only tried the 2N5484 parts. I used a T50-6 toroid as a basis for the main resonator coil and this ended up being around 6uH for oscillation at 5.2MHz. The Idss of these FETs is quite low. Probably only 2mA. However, the circuit does fire up at just over 5MHz and it produces a lot of negative resistance so I don't think loop gain is a problem with these particular JFETs. It seems to work about the same as the simulation. I get 11Vpkpk in the resonator with 150pF in the resonator. The loaded Q simulates to be about 45 but I haven't tried to measure this on the real circuit in open loop. With these numbers I think the resonator power is just over 1mW. The simulation predicts a decent noise figure for the system and I went with 7dB as a reasonable estimate. I guessed the flicker corner at 15kHz.

When entered into Leeson's equation these numbers deliver the phase noise prediction below.To get power out of the circuit I went for a simple L match down to 50R from the JFET drain. This is really a fudge and not ideal. But it did allow me to look at the phase noise on a spectrum analyser at a reasonable power level. My old(ish) Tek RTSA does have a signal source analyser feature built in but it isn't as good as the megabucks Agilent E5052A phase noise analysers we have at work. I can measure down to about -136dBc/Hz at very close offsets but that is the limit of the Tek RTSA. At work the E5052A is capable of measuring down past -175dBc/Hz.

Therefore, with the L match interface, the signal into the RTSA from the Franklin oscillator is at about 200mVrms. You can see in the phase noise plot below that the close in phase noise is very simular to the simulation plot. Also, 200mVrms is a similar RF level to the original requirement in the original post.

At 100Hz the noise is better than -80dBc/Hz, at 1kHz it is better than -120dBc/Hz. However by a few kHz the phase noise floor limit of the analyser is hit at around -136dBc/Hz. So I can't show the phase noise at a 10kHz offset because it is masked by the noise of the analyser. I'd expect it to be somwhere close to -150dBc/Hz when measured on an E5052A SSA but that really is just a guess based on the simulation. I think the reason the phase noise looks lumpy and uneven below 300Hz is because of vibration/microphony effects on my test bench that are making the resonator wiggle about and also because of noise pickup and and maybe some noise/ripple on the power supply.

I've not tried to measure the frequency drift but I'd expect it to be dominated by the T50-6 powdered iron toroid used in the resonator. Also, my workroom isn't very stable from a thermal point of view. I have a fancy shielded enclosure here that might help with some of the noise pickup although I'm not sure how well it works down at low frequencies. It might help with the drift as well because it will keep out any sudden changes in air temperature in the room as I move about and the test equipment gets warmer on this fine evening here in N Glos. However, because I've built the oscillator with a feeble and wobbly layout and a wobbly toroidal resonator it probably isn't worth trying out any stability tests.

I can try measuring the phase noise of the oscillator on an E5052A at work but this won't be possible until next week. The E5052A starts at 10MHz so I'll have to read the manual to see if I can feed it in as a baseband signal. I've never done this before with the E5052A as I 've only ever used it above 10MHz.

[G0HZU_JMR]

Granitehill, have a quick look down the 'LO Noise' and the 'Spacing' columns in the link below. Most radios seem to be tested at a 10kHz offset (spacing) and there are quite a few radios that measure close to -100dBc/Hz at a 10kHz offset. That's probably 50dB worse than this little Franklin oscillator.

http://www.sherweng.com/table.html

I do think the phase noise of this oscillator will be close to -150dBc/Hz at a 10kHz offset but even if the -136dBc/Hz limit of the Tek RTSA analyser is used instead, it is still a lot better than the system phase noise of many HF transceivers of the last 30-35 years from Yaesu/Kenwood. The Yaesu FT One measures -99dBc/Hz at 10kHz offset for example.
I've added some scaling text on the frequency axis in the plot below to make it clearer where the 100Hz, 1kHz and 10kHz offsets are. The marker shows the phase noise is somewhere around -122dBc/Hz at a 933Hz offset.

[Granitehill]

Thanks for the simulation and test data - this will be very useful.
I'm probably going to use 2N4416A FETs - I've got a bagful, so I can select a couple for low Idss (5-15mA spec range). The value of the drain resistors is due a bit of experimentation as well.

The unloaded Q of the resonator I expect to be in the 300-400 range. I've got some excellent (large) silver-wound ceramic coils harvested from old Clansman radios. The variable C will be the capacitor and gearbox from an old BC221 - which I guess is still one of the best precision tuning mechanisms ever. Since you mentioned the use of a T50-6 inductor, I want to try that as well just to get an idea of the comparative temperature stability. It'll be worse, obviously, but just how much will be most interesting.

I think output coupling will be straightforward - I'm not constrained by low component count. Probably a very high impedance source follower with a few pF coupling to one of the drains. A low-pass filter will be on the output, so harmonic output from the oscillator isn't too much of a concern.

Thanks again for all the pointers - I'm now a lot more comfortable that the Franklin is a viable VFO, given some care and component selection. I can see why it's probably not an optimum choice for a production design, though!

[G0HZU_JMR]

Glad the info is useful!

I've spent some time playing with it inside my screened enclosure and I am seriously impressed with the results. The general phase noise performance is fairly predictable and is down to a few basic equations so no surprises there but I did try looking at the drift and I was hoping to see a bit of an improvement in the very close in phase noise down to a few Hz. I've also tacked the toroid down with some RTV to minimise microphony.

My first drift test (inside the screened enclosure) showed about 20Hz drift in about 20 minutes but the nicest surprise was how much the screened enclosure cleans up the bumps in the close in phase noise. The response is nice and linear and is more like the shape of the theory curve. I also took a regular spectrum analyser plot with a 100Hz span to look at how it behaves at offsets below 10Hz. See attached. This is a spectrum span of just 100Hz and it still looks to be jitter free. This is very good I think.

One odd thing is that the phase noise plot now shows lots of energy at 50Hz and 150Hz and 250Hz. I'm not sure how this is happening yet. It even does it with a battery supply so it isn't from the bench PSU and I don't think it is microphony.

One thing I have done with all the recent tests of the real oscillator is I have corrected the circuit for the misaligned gain/phase response I found in my initial simulations. I think the 1k drain resistance does slightly mess things up here. The phase noise benefit of doing this is fairly insignificant but I think it is a good idea to align the peak in group delay in the resonator with the zero phase point around the loop. This ensures that the feedback happens at the point where the phase slope through the resonator is at its steepest. So this should be good for stability (in theory at least).

This is the little screened enclosure I have here.
http://www.ramseyelectronics.com/product.php?pid=5

It is only a desktop enclosure but it has a good spec and seems to work well over a huge frequency range. The connector plate on the back allows easy interfacing to the insides and it seems to be very RF tight.

[G0HZU_JMR]

The unloaded Q of the resonator I expect to be in the 300-400 range. I've got some excellent (large) silver-wound ceramic coils harvested from old Clansman radios. The variable C will be the capacitor and gearbox from an old BC221 - which I guess is still one of the best precision tuning mechanisms ever. Since you mentioned the use of a T50-6 inductor, I want to try that as well just to get an idea of the comparative temperature stability. It'll be worse, obviously, but just how much will be most interesting.

If you end up trying for a high loaded Q, then I'd definitely recommend keeping an eye on the resonator voltage and the RF voltage at the second JFET gate. If you haven't made one already I'd strongly recommend making a classic RF detector probe that feeds to a 10Meg DVM. This probe should be in its element here because it will hardly load the circuit under test and the waveform should be a clean sinewave at the top of the resonator. The (HP2800 or 1N5711 Schottky?) diode should end up being mainly reverse biased once it has detected the RF waveform and the capacitance and resistive loading of the diode should be minimal with large RF waveforms like this. So you should be able to measure the RF voltage quite reliably without loading the resonator significantly. By comparison, a x10 scope probe would be unsuitable because of the capacitive and resistive loading it has up at 11-16MHz.

I think the JFET gate junction will clamp the RF voltage and push it negative. It will conduct a bit on the peak of the waveform which is normally not a nice thing but I don't think it will harm the JFET in this case. However, if you go in pursuit of high loaded Q the resonator voltage could easily rocket up to 40Vpkpk if you start changing the coupling caps or the supply voltage amongst other things. So it could be the case that the reverse voltage at the gate could become stressful for the JFET. As David says, there will be a capacitive divider here with the gate capacitance so the RF voltage should be a bit lower at the JFET. I'm not an expert on JFET physics, we stopped using them at work over 20 years ago so maybe someone else can comment here.

[Granitehill]

I've just come across a bit in G3VA's Technical Topics from June 78 Radcom. This is a Franklin designed by ZL2APC, which seems to have a rather more sensible biassing arrangement than some of the others I've looked at. He uses two 2N4360 P-channel devices, but it would work fine with supply polarity reversals and N-channel devices where appropriate. Well worth consideration, I think.

The use of an RF probe - yes - I've got one so OK there. My Racal 9301A RMS voltmeter with a 10:1 capacitive multiplier on its probe input will also be useful, I guess.

The 50Hz and harmonics you're seeing might be a stray hum field from a transformer affecting the toroid core permeability a little - does your test enclosure have good magnetic field screening, I wonder ?

[G0HZU_JMR]

The 50Hz and harmonics you're seeing might be a stray hum field from a transformer affecting the toroid core permeability a little - does your test enclosure have good magnetic field screening, I wonder ?

I've not done any further tests but I think you may be right. Last night I did try turning off lots of things that were nearby but it achieved nothing. I don't think the enclosure was designed for this type of screening. It's interesting that the 50Hz and 150Hz pickup is so bad. Maybe the enclosure actually makes things worse somehow.

In SSA mode below 40MHz the analyser feeds the test signal direct to the ADC used for its digital IF. So there is no up/down conversion and no LO noise in the analyser apart from the master clock. Therefore, below 40MHz, the analyser's internal phase noise and spurious are minimal. So I can rule out the analyser as the culprit. I think it can measure down below -120dBc/Hz at just a 10Hz offset. This is the cleanest test signal I can give it. By a few hundred Hz offset the limit is the ADC/DSP and it seems to max out at about -136dBc/Hz.

[G0HZU_JMR]

I've just come across a bit in G3VA's Technical Topics from June 78 Radcom. This is a Franklin designed by ZL2APC, which seems to have a rather more sensible biassing arrangement than some of the others I've looked at. He uses two 2N4360 P-channel devices, but it would work fine with supply polarity reversals and N-channel devices where appropriate. Well worth consideration, I think.

Yes, the VE3RF circuit is very simple and seems to work well but I think it could be a bit unpredictable in terms of loop gain (it might not start with some JFETs) and the resonator voltage may vary a lot because of the way it can be so affected by the JFET characteristics. On a simulator the changes I see across 2N5484 through 2N5486 are quite dramatic.

However, I have to say that this lashup version of the VE3RF oscillator I have in the screened box is probably the most stable 5MHz oscillator I've ever made and I've changed nothing on it since the initial build. I did include the subtle phase correction in the initial build. Up at 16MHz I think the gain/phase error will be less because there will be some phase shift in the overall circuit anyway at the higher frequency.

[G6Tanuki]

As a pragmatist, I really feel that this getting bogged-down in wrangling over noise-sidebands and phase-noise for what is really a pretty simple, low-powered radio to be used on the amateur-bands is horribly over-analysing the issue.

OK, if you were to be running 100Kw of carrier-power and you had another station 4KHz higher- or lower, noise-sidebands on your oscillator's fundamental _might_ be an iseue.

But, to be honest, if your on-channel radiated peak-power's only 10 or 20 Watts, and the wibbly sidebands of your oscillator are 30dB down, in these days of low-occupancy of the HF bands.....

**NOBODY'S GOING TO NOTICE**

**OR CARE**.

Build an oscillator!

Make it frequency-stable in the short-term [staying on-frequency for the duration of an 'over']

Put it on-air!

Stop worrying about seriously-marginal spectral-purity issues.

Go out and work the world!

[Radio Wrangler]

Originally Posted by Granitehill

The major unknown would be the noise level. Since the oscillator is running at
low level, would'nt this imply a highish close-in noise spectrum ?
Has anyone got any ideas on this, rather than the more usual Clapp, Seiler, Vackar etc ?

Well, the original post was a question about thoughts on noise content.

You can indeed get away with significant phase noise sidebands on an amateur HF transmitter. Probably no-one will notice.

Try the same dirty oscillator in a receiver, and through the wonder of reciprocal mixing, all the signals in the band will appear to have the same relative level of noise sidebands and this will be at a level that will limit your ability to read small signals close to large ones. Not too bad now unless you're playing in DX pile-ups, but it used to be hellish with the high power broadcasters next door to the 40m band.

David

[Tyso_Bl]

Originally Posted by G6Tanuki

B

**NOBODY'S GOING TO NOTICE**

**OR CARE**.

Build an oscillator!

Make it frequency-stable in the short-term [staying on-frequency for the duration of an 'over']

Put it on-air!

Stop worrying about seriously-marginal spectral-purity issues.

Go out and work the world!

I must say I agree with these sentiments, it's very easy to overthink a project, and get nothing done, I got some interesting results in the past with modulated 807 xtal controlled power oscillators, around 20W output. Goodness only know what the phase noise, etc was like! But it got the job done, and that is waht mattered.

Sol sodder it up, suck it, and see!

[Radio Wrangler]

I'd expect the phase noise to be not too bad, Tyso. A bit of chirp, maybe. A lot of fun. I used to use a 6BW6 power osc with 10XY crystal. Key clicks were the hardest thing to clear up.

David, G-QRP 3252