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Components and Circuits For discussions about component types, alternatives and availability, circuit configurations and modifications etc. Discussions here should be of a general nature and not about specific sets. |
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9th Dec 2018, 7:12 pm | #1 |
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Sipmos MOSFET fails with no gate voltage applied...
A BUZ171, half a complimentary pair with a BUZ172 in a circuit I was putting together, just failed short circuit with no gate voltage applied.
It was configured (obviously) drain-to-drain with the other MOSFET. I'd merely applied the correct DC voltage across (+) the source of the BUZ171 and (-) the grounded source of the BUZ172. There was no load. The transistor must have switched itself on with a spurious but sufficient charge to the gate - no drive was applied -to so it's difficult to see how it biased itself on otherwise. Is this a known problem? These aren't particularly cheap devices so I don't want a repeat.
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9th Dec 2018, 7:38 pm | #2 |
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Re: Sipmos MOSFET fails with no gate voltage applied...
If the gate wasn't connected, it's a well known problem. Gate insulation is so good that charge, one way or the other builds up until the gate protection diode limits it. Depending on the direction of the charge, the FET is biassed full on or full off.
More expensive than tossing a coin. David
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9th Dec 2018, 7:56 pm | #3 | |
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Re: Sipmos MOSFET fails with no gate voltage applied...
Quote:
What’s a workaround? I have 5V1 zeners in the gate circuit to (when it is present) precisely to bias them off decisively , but they were left floating at the time. I don’t want to repeat the experience as if is a royal pain as well as expensive.
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Al Last edited by Al (astral highway); 9th Dec 2018 at 8:22 pm. |
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9th Dec 2018, 7:58 pm | #4 |
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Re: Sipmos MOSFET fails with no gate voltage applied...
There's internal capacitances, Cgs and Cgd. If everything starts off at the same potential, the gate is unconnected, and you apply a voltage drain-source, the MOSFET will start to turn on when Vds > Vth x (1/Cgs + 1/Cdg) / (1/Cgs) by simple capacitive potential divider action.
And once the thing starts to turn on, you can get thermal runaway because Vth has a slight negative temperature coefficient. |
9th Dec 2018, 8:16 pm | #5 | ||
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Re: Sipmos MOSFET fails with no gate voltage applied...
Quote:
Quote:
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Al Last edited by Al (astral highway); 9th Dec 2018 at 8:22 pm. |
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9th Dec 2018, 8:44 pm | #6 |
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Re: Sipmos MOSFET fails with no gate voltage applied...
I will use this experience as an opportunity to solve any remaining problems so it doesn’t happen again.
The below circuit is better as it has dead-time to make it impossible for both power devices to conduct at once (not the original problem) ... only I don’t know how to work out a value for ZD1... The MOSFETs listed aren’t types I’ll be using - instead, generic 150mA 60V types, Vth 2.4V Anyone , please ? The circuit also solves the original problem.
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Al Last edited by Al (astral highway); 9th Dec 2018 at 9:02 pm. |
10th Dec 2018, 8:24 am | #7 |
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Re: Sipmos MOSFET fails with no gate voltage applied...
Bit out of my league here, but I though it as usual practice to put 100r on the gates of mosfets as protection.
Andy.
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10th Dec 2018, 9:06 am | #8 |
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Re: Sipmos MOSFET fails with no gate voltage applied...
I don't know what you are trying to achieve, but that circuit looks less than ideal for most things I can think of. Surely that resistor across the gates tends to produce shoot through current.
What are you trying to do? Last edited by trsomian; 10th Dec 2018 at 9:30 am. |
10th Dec 2018, 10:29 am | #9 | ||
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Re: Sipmos MOSFET fails with no gate voltage applied...
Quote:
Agree - it looks like an "Aaargh!" circuit, with lots of opportunity for Q8 and Q9 to turn on at the same time. Quote:
It also helps prevent fault propagation. If you kill the FETs such that the gate goes internally short-circuit to everything, the gate resistor can blow open and isolate the upstream circuitry, which stands a better chance of surviving. |
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10th Dec 2018, 11:07 am | #10 |
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Re: Sipmos MOSFET fails with no gate voltage applied...
You don't just have to design a circuit to work, you also have to design it to survive being turned on. To survive if one power supply leads or lags others, if signals appear in different sequences etc.
It's the electronic equivalent to the unassembleable mechanical construction. Mosfets are usually provided with a gate-source resistor so they default to off if proper drive is missing, plus other measures. David
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10th Dec 2018, 12:25 pm | #11 |
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Re: Sipmos MOSFET fails with no gate voltage applied...
I have found MOSFETs that can be connected in series with a lamp and will stay on after the gate has been touched with a diode tester. They will stay hard on for some time.
They can turn on and off with static from bits of plastic without a resistor on the gate. |
10th Dec 2018, 12:34 pm | #12 |
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Re: Sipmos MOSFET fails with no gate voltage applied...
Exactly. In fact I have found this to be a good way of testing power MOSFETs, wet fingers between gate and drain and see if it turns 'on' and stays on with finger removed; wet finger between gate and source to see if it turns 'off' and stays off.
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10th Dec 2018, 12:43 pm | #13 |
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Re: Sipmos MOSFET fails with no gate voltage applied...
They are indeed like high power static memory switches without a bleed resistor.
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10th Dec 2018, 1:21 pm | #14 |
Hexode
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Re: Sipmos MOSFET fails with no gate voltage applied...
I can't ever remember a FET with a gate to source resistor, though that doesn't mean they don't exist.
One of the other problems with the circuit shown is that it will put 20V from gate to source of the output devices, which is usually about the absolute maximum for such a voltage. Really needs to be limited to 10 to 12V, well clear of the 20 maximum but still plenty to switch the devices hard on |
10th Dec 2018, 1:26 pm | #15 | |
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Re: Sipmos MOSFET fails with no gate voltage applied...
Quote:
Over a couple of years, I’ve seen many well designed circuits but none quite addressed this except by suggesting using paralleled chips! UCC37321/UCC37322 is a pretty robust pair of chips but does have big ambitions in a small body. So, noting that such IC’s are beautifully designed to overcome all sorts of problems - including the ones on this thread -I decided to investigate the claims made by a couple of authors who say they’ve designed very competent, very high pulse current gate drivers with discrete components. This was just out of curiosity and I don’t think it’s that simple . The circuit you’re asking about appeared herehttps://daycounter.com/Circuits/HV-M...T-Driver.phtml If you scroll down to the bottom of that page, the author describes the switching sequence and why according to the designer it isn’t possible for both power devices to switch on at once .
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Al Last edited by Al (astral highway); 10th Dec 2018 at 1:45 pm. |
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10th Dec 2018, 1:47 pm | #16 |
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Re: Sipmos MOSFET fails with no gate voltage applied...
That’s quite some sensitivity!
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10th Dec 2018, 2:12 pm | #17 | |
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Re: Sipmos MOSFET fails with no gate voltage applied...
Quote:
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10th Dec 2018, 3:02 pm | #18 |
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Re: Sipmos MOSFET fails with no gate voltage applied...
Hi Al,
There is another way to skin the cat. If you don't mind wasting a couple of watts of power. One issue with complimentary output devices is the fact that the drive to each is problematic in that it is referenced to the power supply in one case and ground in the other because of the source connections. Its pretty easy with 5V logic & rail to rail cmos, as easy complimentary output devices like flip flops work as drivers. And of course you can wire up gates with excluded states and dead band circuits that won't glitch even at power up. But for your circuit with the two fets & 20V I would go down another route, it almost looks too simple (see attached). You will have to wind a small trifilar wound transformer good for about 2W at the operating frequency and the windings would need a DC resistance of less than 10 to 20R. The trick is this: Not only do the zeners limit the fet gate voltage to a safe 15V, but when one fet is being driven, the other zener on the other fet is forward biased, loading the other transformer winding with the 220R resistor. So from the transformer's perspective, it is as though it is always loaded with 220R (hence the power wastage) and as it is trifilar wound, with low leakage inductances, the primary damping is good and no damping components are required on the primary for this reason. The Fet's G-S voltages can only ever be extremes of 15V or about 0.7v and best of all, since the transformer output voltage has to cross zero before it can change polarity, the fets can never be on together, even at power up and the source resistance is low enough to discharge the gate capacitances quickly. They can be made lower, like 100R if you don't mind wasting a bit more power, if the fets you had were massive with large gate capactiances. Also, it has the advantage if the drive signal vanishes,due t the AC coupling by the transformer both fets definitely remain off and its pretty immune from trouble at power up. The blue blocks represent the transformer windings, sorry about the rough sketch and it would be worth checking it as I drafted it up quickly. In addition, if you go to a transformer you can get rid of the complimentary fet as you now have isolated drive signals and can just use two Nch fets. It might be a requirement to put a DC bias on the input fet to help keep the drive as symmetrical as possible by having an initial field in the transformer core. (I should have mentioned that the forward conducting zener rapidly discharges the gate before the other fet switches on). Last edited by Argus25; 10th Dec 2018 at 3:25 pm. Reason: typo |
10th Dec 2018, 4:39 pm | #19 | |
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Re: Sipmos MOSFET fails with no gate voltage applied...
Quote:
With really small FETs, it could work. But with bigger FETs, the idea of charging the gate of one via a 1k resistor means that there could be a significant delay between the input changing state, and the output. It's a nasty circuit. If the supply voltage Vs is lower than the Zener voltage of D1, but higher than the sum of the Vth of Q8 and Q9, and the input is Lo, then neither Q7 nor Q11 will be turned on. So Q8 and Q9 gates, together with R10, will be effectively floating. Under such conditions, Sod's law applies and they will float to a mid-point voltage where Q8 and Q9 are both 'on' and you get shoot-thru current. It would be better if D1 wasn't there (straight piece of wire), R11 wasn't there (O/C), R9 and C1 were just replaced by S/C. Then, although during transitions, Q7 and Q11 could both be 'on' the shoothrough of these is limited by R10... and Q8 and Q9 would both be 'off' in the way that the author intended. And there would be no 'funnies' as the supply was wound up. As Trsomian has already observed, 20V is getting high for this type of circuit. 12V is about right, but check Vgsmax of your devices - and it needs to suit the MOSFET you are trying to drive too. |
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10th Dec 2018, 6:01 pm | #20 | ||
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Re: Sipmos MOSFET fails with no gate voltage applied...
Quote:
Quote:
The power devices (IGBTs) I'm driving (through a gate drive transformer) are indeed massive! They are SKM400GB IGBT's, a half-bridge module. If I hadn't spent so much money on them, I'd have changed my mind about the choice by now! Vges=20V Cies=24nF. Qg=4420 nC (per device, two in the module, so double this) Couple this with a higher switching frequency than most inverters (270 KHz or so) and I have quite a few problems to overcome... Since Igate= Ige+ Igc =Qgate * fswitching... I need an average of nearly 60W of drive power. Also I need an average of 1.2A per gate, and peak current of 20A per gate. This is just too much, even for all the bespoke gate driver chips that I can find. Obviously I'm not the first person to face this problem. But I note that development boards with very robust driver circuitry are available, but are very expensive. I had the best success with TC4451 and TC4452. But this was charging only one half of a much smaller IGBT brick with gate capacitances only 7nF instead of 20nF per gate. The heatsink driving one gate was warm, but not uncomfortably so. But when I tried to drive both gates at once, there was a chain reaction... 1) I was using an SMPS (Walwart) with enough headroom to provide this average current. Only I wanted 15V regulated, so was using 20V in. The big voltage regulator that I'd built on my driver board overheated and the chips saw 20V from the SMPS and bang, that was that. They're quite expensive. 2) Most published circuits don't really show what's happening on the DC power supply and don't convincingly prove how these big drivers can be fed enough to take instantaneous gigantic gulps of current. I got round this to drive one gate, but not two of the size I've cited, both at once. I now have some nice low ESR tantalum/ silver caps that are a military spec but there are other considerations, including needing a crowbar to prevent a replica of what I've just described. I know I can, and I will, reduce the duty cycle (probably right down to 10- 25%) but my curiosity is lit-up enough to want to know how to build a circuit that could thoeretically have a 100% duty cycle. So this excursion into (after your circuit) an isolated driver with discrete components really has my attention... Pictured are 1) The build that blew up recently. As I say, this was with the beautiful TC4451/4452 just out of view on the heatsink. 2) The waveform right on the gate. But this isn't my target IGBT. It's half of a smaller half-bridge IGBT module with a gate capacitance of 'only' 7nF per device. The drive voltage is just over 20V peak to peak. In an attempt to drive these big devices hard on, I note that some people go up to 28V. This of course eventually punches a hole in the gate, but apparently only after many operating cycles.
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Al Last edited by Al (astral highway); 10th Dec 2018 at 6:31 pm. |
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