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Old 3rd Jun 2020, 10:13 pm   #41
G0HZU_JMR
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Default Re: LO for genuine 10m FM10D Pye Cambridge

I've still not had time to look at this again but my spreadsheet predicts that 35.000MHz will be quite a clean frequency.

The nearest 'poor' frequency isn't far away. Try 35.010MHz and I think there could be sidebands at 50kHz, 100kHz and 150kHz. Try 35.020MHz and the sidebands should expand to 100kHz, 200kHz and 300kHz.

The spreadsheet predicts that (at these frequencies) harmonics of the 25MHz clock interact with harmonics of the wanted output frequency. In other words I think that there will be beat notes fairly close to the wanted carrier and these are partly happening due to the PCB layout. I think it may be possible to change to a remote 25MHz reference clock and maybe even dampen the edges of the clock slightly with an RC network on the PCB. These sidebands may get lower.

They may appear at quite a low level so you way need to increase the level into the analyser and also reduce the span/RBW to see them.

There are output frequencies where this effect is more pronounced. Also I think the PLL has a loop BW of about 50kHz according to the phase noise plots by KE5FX and the impact/level of the beat notes will depend on where they appear with respect to the loop cutoff frequency.
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Old 4th Jun 2020, 9:31 am   #42
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Default Re: LO for genuine 10m FM10D Pye Cambridge

Thanks for the comments Jeremy. In my case the ref Xtal is 27MHz rather than 25MHz so maybe this window will occur around 37.8MHz instead?

I still have to look into ensuring that only the wanted PLL and dividers are enabled. There are quite enough registers to program to get the divisions you do want without worrying about other parts of the chip you do not need. If, for example, the other PLL is running and doing it's own thing by default then crosstalk could be responsible for some spurs.

The 35MHz output had worst spurs of -65dBc at 11dBm output level. (see picture in previous post - there is a 10dB pad between Si5351 and SA) The spurs change spacing depending on tuned frequency. I have yet to see if changing output drive strength affects their level. I don't think it will - they will scale down 1:1 with wanted carrier. I think I could live with this spur level on an RX LO for amateur use all the same.

Dividing the 35MHz by 3 to give an output around 11.8MHz made the -65dBc worst spurs go down to better than -75dBc. I suppose thats to be be expected and you have won nothing if the RF board is only made to multiply back up again.
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Old 4th Jun 2020, 10:59 am   #43
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Default Re: LO for genuine 10m FM10D Pye Cambridge

If your system clock is 27MHz you could try programming the Si5351 output to 34.71MHz as an experiment. A quickly amended (27MHz Fclk) version of the spreadsheet predicts sidebands at +/-30kHz at this frequency.

The sidebands would probably move to +/-250kHz if the frequency was changed to 34.75MHz.
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Old 4th Jun 2020, 3:42 pm   #44
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Default Re: LO for genuine 10m FM10D Pye Cambridge

Thanks. I'll take a look as soon as time permits. I will have to recompile since it falls outside working range at the moment (35.2 to 35.7MHz) but that is a small change to make.
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Old 5th Jun 2020, 3:25 pm   #45
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Default Re: LO for genuine 10m FM10D Pye Cambridge

I did the recompile this afternoon.

Yes just around 34.71MHz the highest level spurs (-62dBc) come in to zero beat the carrier reappearing again as you tune lower. There are further spurs at ~+/- 3.9MHz and +/-7.8MHz visible (approx).

At 34.75MHz the zero beat spurs appear at the same level and about +/- 230kHz away. The 27MHz is of course not perfect here which will explain small differences in frequency.

Tuning higher the spurs move further away and they also seem to drop in level slightly.

Just for fun I added a line to also program PLL B with the same frequency data so I could be sure it would not be running somewhere else and causing spurs. No visible difference for that.
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Old 6th Jun 2020, 1:55 pm   #46
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Default Re: LO for genuine 10m FM10D Pye Cambridge

Thanks. That seems to be doing what the spreadsheet predicted and the spurs don't seem to be that high.

I had another play this morning and I think I can now program my Si5351 to any frequency in its range.

I tried 2.46666MHz which is 29.6MHz divided by 12. I fed this into my Tek spectrum analyser to look at the close in phase noise and the result is as below. This analyser has an exotic option fitted that allows it to act as an ultra low noise signal source analyser for frequencies below 40MHz.

So the noise plot below should be mainly due to the noise from the Si5351. The result seems to be slightly cleaner than the plots by KE5FX but I think I'm using a different drive current from the Si5351. However, above about 50kHz I think there will be some contribution from the analyser so the sums below might not be representative of what the multipled performance will be...

As you know, when multiplied up by N=12 this should raise the noise by 20*logN so you can expect to see phase noise 21.6dB higher than the plot below once you multiply up to 29.6MHz.

This will be OK I think because your multiplier stages will be tuned/narrow and so the phase noise at (say) 100kHz offset would hopefully be better than the -142 + 21.6 = -120dBc/Hz you might see from a wideband multiplier at this offset.
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Old 6th Jun 2020, 2:06 pm   #47
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Default Re: LO for genuine 10m FM10D Pye Cambridge

At work I have access to a couple of E5052A signal source analysers and these would be able to do a much better job of analysing the phase noise. Sadly, I'm restricted to working from home so I can't easily do this test. I'm now not even allowed inside the building without applying in writing for a 1 day access pass. Hopefully this will change soon assuming I don't get furloughed or made redundant.

I can try plotting the noise with the Tek analyser up at about 35MHz but because my Si5351 PCB uses a 25MHz clock any discrete spurious terms will obviously be at different offsets to your board with the 27MHz clock. I think the phase noise profile should be comparable despite the clock difference so it might be worth trying.
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Old 6th Jun 2020, 2:11 pm   #48
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Default Re: LO for genuine 10m FM10D Pye Cambridge

Thanks for all the effort Jeremy. It would be intersting to see if your general spur situation is roughly the same even if we have different ref freqs...eg that the spurs you predicted (which have been the highest in level seen so far) are also about -62dBc. As you say the general phase noise should be roughly the same.

Curious to know how you programmed the generation of 2.466666 please?
I am doing that by generating 29.6/3 using PLL_A and Multisynth0 then an output divider of 4. Of course it could be done by generating 2.466666 and not using the output divider at all. It might be interesting to see if there is any advantage one way or the other.
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Old 6th Jun 2020, 2:20 pm   #49
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Default Re: LO for genuine 10m FM10D Pye Cambridge

For 2.46666MHz I used the settings suggested by the SiLabs clockbuilder program as below.

PLL A
Input Frequency (MHz) = 25.000000000
VCO Frequency (MHz) = 695.599900000
Feedback Divider = 27 205999/250000
SSC disabled

Output Clocks
Channel 0
Output Frequency (MHz) = 2.466666666
Multisynth Output Frequency (MHz) = 2.466666666
Multisynth Divider = 282
R Divider = 1

PLL source = PLLA
Initial phase offset (ns) = 0.000
Powered down = No
Inverted = No
Drive Strength = b11
Disable State = Low
Clock Source = b11
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Old 6th Jun 2020, 2:35 pm   #50
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Default Re: LO for genuine 10m FM10D Pye Cambridge

Thanks. It's as I thought. R Divider =1 when in my case it is 4.

I doubt it matters since the spurs happen in the PLL and it doesn't matter where you divide, only by how much.
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Old 6th Jun 2020, 3:08 pm   #51
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Default Re: LO for genuine 10m FM10D Pye Cambridge

Here's a few plots at 35.020MHz. With a 25MHz clock this output frequency should have spurious terms every 100kHz in theory and this looks to be the case. The phase noise is about 20dB higher in general. The SSA function in the Tek analyser isn't very good at recording the levels of individual spurs, I think it is best suited for noise. Therefore, I've included a regular analyser plot and this shows the spurious terms every 100kHz. I've also included a spectral plot of a Marconi 2024 sig gen at the same frequency. This looks to be very clean compared to the Si5351.

Overall, I think the Si5351 phase noise and spurious will be fine for a 10m FM radio for both Tx and Rx. Purists might not be happy if that LO was used down on the 40m band but I think it will be OK on 10m. It's similar or better than the LO used in the Uniden HR2510 or 2830 10m radio (President Lincoln).

This Uniden CB/10m radio puts out a very wide -126dBc/Hz noise pedestal across 25-30MHz on transmit and I think I'm the only person who has ever noted or commented on this issue with this radio. I don't think your Pye conversion will give out such a wide noise pedestal spanning several MHz. It might be similar for offsets out to 100kHz but not much further.
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Old 6th Jun 2020, 4:40 pm   #52
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Default Re: LO for genuine 10m FM10D Pye Cambridge

Nice plots. Interesting your highest spurs are at 70dBc.
I rather agree that I'm inclined to try this. The RX performance will certainly be no issue. (And doesn't that Marconi look nice!)

On TX I think I will be lucky if I can use the full 500kHz of tuning range without power dropping off. We will see. I need to see about interfacing it.

On RX there is a transistor colpitts. I plan to remove the Base to Emitter capacitor and inject where the crystal would have been. The TX is also a Colpitts, one half of a 12AT7.
I will probably do much the same there adjusting the drive for similar grid current. I wonder if there will be enough?.
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Old 6th Jun 2020, 5:29 pm   #53
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Default Re: LO for genuine 10m FM10D Pye Cambridge

I am using the centre output #1 from the Si5351 as it is the shortest and I did also cut away the (unnecessary) #1 track on the PCB underside that folds back to the SIL connector near the crystal oscillator.

I'm not sure if this helped with the spurious on these plots but it did seem to help when I was using a high impedance probe. All the plots I've shown are via a dc block straight into the 50R analyser.

The spurs appear more plentiful if I start hunting for worst case and I look on wider spans and this seems to happen up around 39MHz. The frequency range of the Tek analyser is kind of split between 0-40MHz and 35-8500MHz so it has a bit of a gap in its capabilities at around 40MHz and it can't show wide spans when the centre frequency is near 40MHz.

See below for a 10MHz wide plot at 38.9MHz using a different spectrum analyser. This was a really nice analyser back in its heyday. Possibly the best available at the time.

This does look quite dirty but if I were to look at it with something like a classic HP8568B or HP8566B on the default settings it would look less scary as these old analysers will mask some of the terms with noise and the bell shaped analogue RBW filter would hide some of the others.
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Old 7th Jun 2020, 10:55 am   #54
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Default Re: LO for genuine 10m FM10D Pye Cambridge

Quote:
On TX I think I will be lucky if I can use the full 500kHz of tuning range without power dropping off. We will see. I need to see about interfacing it.
One thing to be wary of will be the wideband noise from the Si5351. On Tx I think it would be worth fitting a very basic 2.5MHz BPF after it. Otherwise there is the risk of the out of band noise mixing back into band in the first multiplier and this would degrade the close to carrier phase noise.
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Old 7th Jun 2020, 10:38 pm   #55
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Default Re: LO for genuine 10m FM10D Pye Cambridge

I reloaded the code for 35.6MHz as this would be the LO frequency for 29.6MHz receive if the system clock was 25MHz. The result on a 10MHz span is shown below. This still gives a lot of spurious terms and I expanded the search range of the sprog hunting spreadsheet and it was able to predict every one of the spurious terms in the plot below and which ones would be the largest.

I'm not sure yet what can be done about this. One possible thing to try is an external clock oscillator that clocks the Si5351 with slower edges and with a bit less amplitude. It might be possible to turn down the drive level of the external clock to the chip. This assumes that an external clock will work OK.

I might have a go at this but it won't be until next weekend at the earliest. It might not achieve anything.
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Old 8th Jun 2020, 9:45 am   #56
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Default Re: LO for genuine 10m FM10D Pye Cambridge

I would be interested to know the various spur terms you identified Jeremy.
My code to calculate the PLL frequencies and the various division ratios is "lifted" from someone who went before and I expect it does little to minimise spurs.

I was thinking about making everything in the PLL pure integer division. This could be quite easy for 10m. The range I wanted 29.3-29.7 in 1kHz steps can be achieved by a division by 30 from the PLL running 876-891MHz in 30kHz steps. 27MHz crystal will generate 30kHz by dividing by 900. PLL is within the allowable range of 600-900MHz and we have no fractional N goings on.

Unfortunately the same trick for LO high by 6MHz =35MHz runs out of PLL range.
I'm thinking that it probably doesn't matter running LO low side (might check the mixer spurs for this) because then the PLL runs 23.2*30 to 23.7*30 and that is 696-711 MHz and back in range.

It might be worth changing my code just to see if there is any merit in this.

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Old 8th Jun 2020, 6:45 pm   #57
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Default Re: LO for genuine 10m FM10D Pye Cambridge

All of the spurs appear to occur on a 10MHz span when ABS(N*RFout +/- M*Fclk) <= 5MHz.


For example the spurious terms at a 3MHz offset appear to be a beat between 5*RFout - 7* Fclk because (5*35.6)-(7*25) = 3MHz.

The spurious terms at a 3.8MHz offset appear to be a beat between 2*RFout - 3* Fclk because (2*35.6)-(3*25) = -3.8MHz.

The spurious terms at an 800kHz offset appear to be a beat between 7*RFout - 10* Fclk because (7*35.6)-(10*25) = -0.8MHz.

The lower level spurious terms appear when N and M get quite large but there may be other mechanisms that generate these terms. However, if I pick up the PCB and press it with my fingers these spurious terms tend to change in amplitude so I think it may be possible to make the levels go down with a change in the PCB layout or a change to the way the 25MHz clock gets generated and fed to the Si5351.
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