Non-working Commodore PET 3016

[ScottishColin]

They should all be there. For example where I said.

Pin 18 - 2.81 / 2.87

The first reading is from UB3 and the second from UC3. Does that make sense?

[ScottishColin]

OK - graphs attached with before and after pin 16 has been cut.

I'm well out of my depth here (can you tell?). Why does 6502 pin 19 have a graph at all if pin 16 is cut? I thought that it would be driven by UB3, or is it the other way around? And if it is, how come UB3 pin 16 has a graph if the pin is cut?

Confused of Perth.

https://drive.google.com/file/d/1iW7...ew?usp=sharing

Colin.

[Timbucus]

The 6502 drives the buffer chip INPUT which outputs a drive on pin 16 to other chips - the stump of the pin on the buffer chip should still show something which I think is what your second trace is showing and you will note is much more like the other signals the last time you did it although still not fully low which concerned Mark.

The last trace shows that the line is pulled high by something on the motherboard when the chip is not in circuit which is strange as I was expecting something to pull it low as before the graph seemed to indicate that would happen as the line seemed to struggle to get very high.

[ScottishColin]

Would it be OK if I desoldered the stump of pin 16 so I can be more sure about the readings I get from the remainder of pin 16 on the IC?

[SiriusHardware]

As per Tim, the 6502 pin drives U3 input and the corresponding output on U3 should carry more or less the same signal.

When it was still connected to the BA10 line UB3 pin 16 still looked quite bad, although disconcertingly different to the way it looked when we first saw it.

Now that you have disconnected it from BA10 it looks much the same as the other lines, which on the face of it suggests that it is not UB3 pin 16 but something else on the BA10 line which is causing that specific problem on BA10.

The question is, do we accept those logic levels coming out of all 16 of the buffer outputs as 'normal'? If not, we are saying that both buffer ICs have failed in the same remarkably uniform way, and it still does not address the question of why UB3 / pin 16 output looks more broken (when connected) than the rest.

Colin: No problem with removing the lower part of UB3 pin 16, you can always replace it with a fine piece of wire if necessary.

[Timbucus]

The effect that Jerry mentions is a lack of drive strength so - it could be they both have the same failure mode. The fact it has recovered would be consistent as only that line from what I can see has a three chip fanout so would suffer greater distress.

[SiriusHardware]

On following BA10 out of the UB3 buffer I find that it appears to go to UE5 (Only) in the RAM area (circuit sheet 5) and UD6, UD7, UD8, UD9 in the ROM area (circuit sheet 4).

While UE5 is soldered I believe all of the UD6-UD9 ICs are in sockets, so how about we temporarily reinstate the UB3 pin 16 connection and remove UD6, UD7, UD8, UD9, taking careful note of where each one goes, then power on and see if the output from UB3 pin 16 looks distressed / looks OK?

If it looks OK, replace UD6 through UD9 one at a time, each time checking to see if the most recently inserted IC is causing the output on UB3 pin 16 to look distressed?

[SiriusHardware]

Crossed with Tim: Well then, what say we, replace the buffers because we can't be sure if that output from them is normal, we don't think it is and the only way to prove it is to change them?

[Timbucus]

It also goes to a chip on the same sheet related to Chip Select - so actually that is driving 6 chips - I counted the ROMs' as 1 really which was silly.

We could really do with a scope of a similar arrangement on a working PET to understand what they look like - we know for example on the MK14 that stuff does not go fully low... whereas on my Triton I know the other sides of the Buffers are truly down at zero.

I am only half paying attention at the moment - do we know where the pullup for BA10 comes from?

[ScottishColin]

Originally Posted by SiriusHardware

On following BA10 out of the UB3 buffer I find that it appears to go to UE5 (Only) in the RAM area (circuit sheet 5) and UD6, UD7, UD8, UD9 in the ROM area (circuit sheet 4).

While UE5 is soldered I believe all of the UD6-UD9 ICs are in sockets, so how about we temporarily reinstate the UB3 pin 16 connection and remove UD6, UD7, UD8, UD9, taking careful note of where each one goes, then power on and see if the output from UB3 pin 16 looks distressed / looks OK?

If it looks OK, replace UD6 through UD9 one at a time, each time checking to see if the most recently inserted IC is causing the output on UB3 pin 16 to look distressed?

Ok - remove UD6, UD7, UD8 and UD9 from their sockets. Reinstate UB3/16 and test/record the signal on UB3/16.

Then reinstate the ICs one at a time to see if it affects the UB3/16 signal.

That right?

[Timbucus]

Originally Posted by ScottishColin

Ok - remove UD6, UD7, UD8 and UD9 from their sockets. Reinstate UB3/16 and test/record the signal on UB3/16.

Then reinstate the ICs one at a time to see if it affects the UB3/16 signal.

That right?

Yes this seems the best approach then it could be one of the other two chips and we can perhaps eliminate them as well if it is still distressed with UD6-9 out.

[SiriusHardware]

Are you referring to the last capture in Colin's link, which appears to show 6502 A10 looking normal but BA10 (after being cut away from UB3 pin 16) riding high? Not sure, but don't TTL inputs traditionally float high if not specifically driven?

As we don't appear to have a similar machine among us to make comparisons with I think that avenue is closed, unless you can draw on your extraordinary information mining skills to find us a full set of system waveforms somewhere.

Which brings us back to the question, replace the buffers, or try some other thing?

Although most of the devices which are driven by BA10 are in sockets, you may be right, if the drive out from UB3 pin 16 is just weak then what we may see is that the more devices we plug back in, in any order, the worse the signal looks.

[SiriusHardware]

On consideration, and following my own advice of 'always try everything you can before spending more money', let's do that-

-Reinstate UB3 pin 16 connection
-Remove UD6 through UD9, remembering where each one goes
-Power up and see if the output of UB3 pin 16 is distressed / is not distressed.

If it is not distressed, replace each of UD6 to UD9, checking the output of UB3 pin 16 after each reinsertion.

If it starts off not distressed and becomes distressed when you have one or more of UD6 to UD9 in, try to work out if it is just one of those ICs which causes the effect or if it is related to the number of ICs you have inserted.

Edit, Ah yes, I missed where BA10 and several other lines circle round and go up to the top left of sheet 1.

[Timbucus]

Originally Posted by SiriusHardware

Are you referring to the last capture in Colin's link, which appears to show 6502 A10 looking normal but BA10 (after being cut away from UB3 pin 16) riding high? Not sure, but don't TTL inputs traditionally float high if not specifically driven?

Yes you are correct sorry - due to the pullup resistor it seems on the input transistor base - it is CMOS that cannot be left to float like that.

I assume it can have a failure mode where that goes almost short which would give us the effect we are seeing.

[SiriusHardware]

If that were the case (very low resistance between +5V and BA10) I think Colin's resistance measurements earlier would have caught that.

It would have been quite difficult for the UB3 pin 16 signal to be what it was the first and second times it was scoped if there was a near irresistable force trying to pull that line high.

[Timbucus]

Originally Posted by SiriusHardware

If that were the case (very low resistance between +5V and BA10) I think Colin's resistance measurements earlier would have caught that.

It would have been quite difficult for the UB3 pin 16 signal to be what it was the first and second times it was scoped if there was a near irresistable force trying to pull that line high.

Ah yes - I said I was only paying partial attention - thanks I missed the resistance checks to +5v. Well it may just be the ability to drag them down then - ergo the buffer is weak on driving low - anyone know the LS output circuit well as to why that could happen?

[Mark1960]

Does the video circuit of the pet drive the buffered address bus, or is there a separate interface to video ram?

[SiriusHardware]

anyone know the LS output circuit well as to why that could happen?

No, I've never opened one up to have a look. I always just treat them as black boxes.

[SiriusHardware]

Originally Posted by Mark1960

Does the video circuit of the pet drive the buffered address bus, or is there a separate interface to video ram?

On first glance the video RAM address bus (SA....) is separated from the buffered address lines (BA....) by 3 * 74LS157 ICs, circuit sheets 7/8 here. The inputs to the 157s are on the BA... lines (so if your question is can the video circuitry drive the BA... lines - it doesn't seem so). And only BA0 to BA9 are involved, BA10 upwards don't go there.

http://www.zimmers.net/anonftp/pub/c...N/320349-7.gif

http://www.zimmers.net/anonftp/pub/c...N/320349-8.gif

[Slothie]

Originally Posted by Mark1960

Does the video circuit of the pet drive the buffered address bus, or is there a separate interface to video ram?

The counter chain that generates the address for the video RAM and the CPU address are fed into a multiplexer that goes to the video RAM ony. There is no way for the current video ram address to get onto the cpu address bus as the video RAM is completely seperate from the system RAM, the CPU just sees a "window" at $8000 to access it.