|
Components and Circuits For discussions about component types, alternatives and availability, circuit configurations and modifications etc. Discussions here should be of a general nature and not about specific sets. |
|
Thread Tools |
14th Dec 2018, 4:54 pm | #61 |
Dekatron
Join Date: Nov 2006
Location: London, UK.
Posts: 3,496
|
Re: Sipmos MOSFET fails with no gate voltage applied...
Nice illustration, Hugo.
I'm aware of the Fourier series and also the additive determination or synthesis, rather, of square waves, using odd harmonics... It would be interesting to see what highest harmonic is determinable in the suitably clean square wave that I eventually pass for service in gate driving. I have a pretty basic digital oscilloscope with only 25MHz bandwidth. It does have a Fast Fourier Transforms (FFF) function but I've never investigated that. It'll go on my list of things to investigate.
__________________
Al |
14th Dec 2018, 7:18 pm | #62 | |||
Dekatron
Join Date: Feb 2007
Location: Lynton, N. Devon, UK.
Posts: 7,087
|
Re: Sipmos MOSFET fails with no gate voltage applied...
Quote:
Quote:
The driver device does need to be 'on' or 'off', if it's passing standing current, that's just a waste. Similarly, the transformer's winding resistances need to be really low - extra resistance just limits the gulps of charging current into the gates of the driven devices, as well as wasting power. Quote:
Totally agree with Hugo that you need to get it working driving nothing at all, then load it with the representative FETs or IGBTs. You could simulate these with little capacitors, maybe starting at 470pF and progressively doubling the value till you get to 24nF. |
|||
14th Dec 2018, 7:39 pm | #63 | |||
Dekatron
Join Date: Nov 2006
Location: London, UK.
Posts: 3,496
|
Re: Sipmos MOSFET fails with no gate voltage applied...
Quote:
Quote:
Quote:
[QUOTE=kalee20;1101501,,Kalee reckons that trying to charge a gate capacitance of 24nF from 0V to 10V in 100nsec needs a current of I = C x dV/dt =2.4A [/QUOTE] True for average current, surely...but peak current is way higher for the big IGBT bricks with the switching time I showed in the photo? [Cies=24nF. Qg=4420 nC from the manufacturer's datasheet] by another method, IgatePeak= (VgateOn-VgateOff)/R(gate resistor external)+R(gate resistor internal) Vgate on=24V Vgate off=-24V Rgate external= 3r3R Rgate Internal=0R1 So IPeak=48/3.4=14.1A per device, or approx 30A altogether!.
__________________
Al Last edited by Al (astral highway); 14th Dec 2018 at 8:08 pm. |
|||
14th Dec 2018, 10:06 pm | #64 |
Moderator
Join Date: Mar 2012
Location: Fife, Scotland, UK.
Posts: 22,894
|
Re: Sipmos MOSFET fails with no gate voltage applied...
Zetex was bought out by "Diodes inc." some but not all of those giant-killing ZTX transistors are still made.
David
__________________
Can't afford the volcanic island yet, but the plans for my monorail and the goons' uniforms are done |
14th Dec 2018, 11:31 pm | #65 | |
No Longer a Member
Join Date: Oct 2016
Location: Maroochydore, Queensland, Australia.
Posts: 2,679
|
Re: Sipmos MOSFET fails with no gate voltage applied...
Quote:
One thing that would also help too, but it is not plainly obvious building a switching circuit, is that if you did re-attempt a class A or single ended driver stage, one way to be sure that the collector current (transformer primary current) and the bias (operating point) of the stage is correct, is to operate it in an analog mode with lower signal level sine wave inputs from the test generator. This way you can view the drive voltages as half sine waves before clipping. Then you can adjust the bias so that the operating point is symmetrical for the drive to each output device prior to clipping. This symmetry is masked over of course when it is driven into clipping and square wave mode, which is the way you intend to use it. |
|
15th Dec 2018, 6:24 pm | #66 | |
Dekatron
Join Date: Feb 2007
Location: Lynton, N. Devon, UK.
Posts: 7,087
|
Re: Sipmos MOSFET fails with no gate voltage applied...
Quote:
Once the gate is charged or discharged, no current at all flows. It's just during the transition that a big gulp of current is demanded. I suspect that the 24nF is only part of the story, and there's significant Cdg (or Miller capacitance), which is why the total gate charge figure is given. Certainly, shifting 4420nC in 100nsec needs a current flow of 4420nC/100nsec = 4.4A. If you want to switch it in 50nsec, you need double that. The presence of series resistors can't change that, but what resistance can do is limit the current, if your drive circuit slews the voltage significantly faster. Just looking at the figures, though... Why do you want to swing from -24V to +24V? Most MOSFETs are fully specified at 10V, and have maximum gate voltages 20V. Equally, there's nothing to be gained taking the gate negative (although direct drive from a transformer can't avoid doing this). I had assumed a swing of 0 to 10V which is 4.8 times easier than -24 to 24V! |
|
16th Dec 2018, 12:52 am | #67 | |
No Longer a Member
Join Date: Oct 2016
Location: Maroochydore, Queensland, Australia.
Posts: 2,679
|
Re: Sipmos MOSFET fails with no gate voltage applied...
Quote:
|
|
16th Dec 2018, 8:29 am | #68 | |
Moderator
Join Date: Mar 2012
Location: Fife, Scotland, UK.
Posts: 22,894
|
Re: Sipmos MOSFET fails with no gate voltage applied...
Quote:
David
__________________
Can't afford the volcanic island yet, but the plans for my monorail and the goons' uniforms are done |
|
17th Dec 2018, 5:17 pm | #69 | ||
Dekatron
Join Date: Feb 2007
Location: Lynton, N. Devon, UK.
Posts: 7,087
|
Re: Sipmos MOSFET fails with no gate voltage applied...
Quote:
[There could be some merit in keeping gate voltage of an 'off' device negative - it would give added immunity to spurious conduction if some external agency imposed a high positive voltage slew on the drain. But that's really almost another subject!] The post # 24 circuit does drive the two FETs by completely different mechanisms: When the driver FET is turned 'on', the 20V supply is snapped across the whole primary. Immediately, therefore, 20V appears across both secondaries. One secondary reverse-biases its Zener via its 240Ω resistor (which therefore dissipates 1.55W). The other charges the FET gate capacitance, which for sake of argument we'll assume is 24nF, till the Zener diode clamps. The time to charge 24nF through 240Ω from zero to 15V is given by: 15 = 24 x (1 - exp(-t/RC)) and with R = 240Ω and C = 24nF we get t = 5.6μsec, so not very fast. When the driver FET is turned 'off' the primary is effectively open-circuit, so overall there is just a LCR circuit comprising the transformer's magnetising inductance (L), the two gate capacitances (C) and the two series 240Ω resistances (R), slightly complicated by the diodes. The waveform on the gates will then be part of a sine-wave, arrested by the clamping action of the diodes. If the transformer had built-up just a bit of magnetising current by the 'on' time not being very long, then the rise-time on the gates in the other direction could be slow - indeed, full drive may not be attained. If on the other hand, there had been oodles of amps built-up, the drive could be very rapid - but it would need a transformer with high energy storage capabilities (alternatively, a high Vμsec product). Deriving design equations for the transformer is possible, but it inherently depends on the 'on' and 'off' times so cannot be regarded as a general-purpose driver in the same way as a IC driver can be used from switching periods of microseconds to days. I have used a circuit similar to Hugo's - with no secondary diodes, much smaller series resistances, and with the addition of an energy-recovery winding - at 75kHz, for duty cycle variable from about 20% to a shade under 50%. As a drive circuit, it runs cool and is efficient. But at very low duty cycles, the 'off' switching speed is lousy slow. |
||
17th Dec 2018, 10:40 pm | #70 | |
No Longer a Member
Join Date: Oct 2016
Location: Maroochydore, Queensland, Australia.
Posts: 2,679
|
Re: Sipmos MOSFET fails with no gate voltage applied...
Quote:
However, there still would be more power loss than with BJT's though. This is because in the case of a BJT the transformer secondary voltages only needs to be around a few volts to establish a fairly consistent drive current in the series base resistors on each half cycle, so the power loss is lower when a half cycle is shunted by its series resistor and diode represented by the base-emitter junctions. |
|
19th Dec 2018, 10:54 am | #71 | |
Dekatron
Join Date: Feb 2007
Location: Lynton, N. Devon, UK.
Posts: 7,087
|
Re: Sipmos MOSFET fails with no gate voltage applied...
Quote:
Biasing in Class A however is really not the way forward in a switching circuit. When the driver device turns 'off-ish' there is no virtue in having a few milliamps flowing - you are effectively then just biasing the transformer core with DC (which isn't transferred to the secondary), so you might as well move the Class A operating point down by that many milliamps so that when 'off-ish' the current flow reaches zero. And then you realise that 'off-ish' is REALLY the same as a solid 'off'. And on the opposite half-cycle, there is no virtue when the driver is 'on-ish' having a few volts remaining across the driver. It just wastes power. You might as well reduce the supply voltage to the driver stage by that many volts and have the driver device hard 'on' rather than 'on-ish'. The transformer primary won't notice any difference! Or alternatively, if your supply voltage is fixed, alter the transformer turns ratio to use ALL the voltage: use the design flexibility that a transformer can give you. The symmetry aspect - if the driver was to operate in class 'A' then the switching 'off' will be no different if the driver is reduced to zero current rather than a standing few milliamps. The switching 'on' WILL be different if the device is operated as a hard switch rather than as a step-change constant current device. But then I'd be thinking, why have a soggy switch-on when a harder switch-on can be achieved? |
|
31st Dec 2018, 1:39 am | #72 |
No Longer a Member
Join Date: Oct 2016
Location: Maroochydore, Queensland, Australia.
Posts: 2,679
|
Re: Sipmos MOSFET fails with no gate voltage applied...
Hi Al,
I was looking at an 8 pin IC the AM0026, that drives the clock inputs on the 8080 CPU in my Sol-20 computer, I didn't think it would be much of a power device. Then I discovered it was the same as a DS0026 and looked up the data sheet. What I saw made me think of you. This IC has the ability to drive high capacity loads (20nS for a 1000pF load) and swings 20V and has a peak drive current of 1.5A and it interfaces to TTL. It would be good perhaps as a driver for some of the medium power fets leading to the massive output ones you plan to use: http://images.100y.com.tw/pdf_file/DS0026.pdf |