FET selection

[G0HZU_JMR]

Can't you just simulate it on a freebie simulator like SimetrixIntro and you will see that you must be doing something wrong?

The simulator will show you how sensitive the circuit is to the operating point and it will show you that you can get a flat response to 200MHz. Note that the operating point for flat response at RF isn't the same operating point that gives the best bootstrapping down at LF. If you set the operating point such that all the negative resistance disappears you will get about 2.5pF input series capacitance at RF frequencies in series with maybe 10 to 130R resistance depending on frequency.

if you set the operating point for best LF bootstrapping there will be a downward slope in frequency to 200MHz and there will be a lot of negative resistance at the input. i.e. the S11 plot on the smith chart will go outside the smith chart circle and this is a sign the probe can go unstable with certain test circuits presented at its input.

Here's an image of my version being tested on a VNA. It took a few minutes to build and it worked first time. Flat to 200MHz just like the simulation. The scale on the VNA is 0.2dB./div. I'm not used to working with leaded components as nearly all my RF experience over the last 25 years has been SMD but you can see that I built it using 'big' leaded parts and I modelled it like this and it still worked OK. It looks very flat to me

Note that the VNA plot taken below is a full two port measurement with the reference plane set at the pin end of the SMA connectors. So it measures the input capacitance here without measuring the capacitance of the SMA connector itself.

[G0HZU_JMR]

See below for what happens if the operating point is set too high or too low or for a flat response. In one plot the response is droopy at low frequencies, the other it is droopy at high frequencies (with lots of negative resistance) and in one plot the response is flat. In the plot that slopes downwards you can see the S11 plot has gone off the smith chart indicating negative resistance. The marker shows -265R for the real part of the impedance at about 50MHz.

The Genesys harmonic balance and linear simulator does the same thing. So does the SimetrixIntro SPICE simulator and so does the RFSIM99 simulator if I feed it s2p files at different operating points for the JFET.

[G0HZU_JMR]

The project I started with in this context was an RF voltmeter supposed to work from '100kHz to (at least) 150MHz', but that used nothing more than a humble 2N3819, with no source follower ahead of the DC amplifier, strung out on a fairly "casual" PCB (see attached PDF).

That design seemed to have some "heritage", but it didn't work for me, and after following this thread, I wonder if it's worked for anyone .

I didn't initially comment on this RF voltmeter circuit because it has so many technical issues/flaws that it simply isn't worth building or even simulating. It looks to be in a nice box with nice construction and a lovely big meter dial but the circuit design is not good unless you just want a meter that moves when RF is fed to it and the movement is roughly consistent for certain RF levels across certain frequencies. But it isn't going to work well at low drive levels and I'd question the performance over temperature here as well.

[G0HZU_JMR]

Here's the plot from a basic SPICE simulation that includes the stray inductance for the 100nF caps and the layout etc. It also shows a flat response for the circuit once the operating point is set for a flat response. It uses a 2N4416A and a BFS17 for the BJT.

I've also included a word doc below showing the VNA measuring the real (ESR) and imaginary parts of the impedance of a microwave capacitor quite accurately up to 3GHz. I've measured a 3.3pF ATC 800B ceramic cap from 500MHz to 3GHz and compared it to the official ATC measurement data for the same 800B 3P3 cap. Their self resonance at just under 3GHz is slightly different to mine because I've used a very tight 1 port test fixture and they have created a 2 port model in a different fixture. But the results are very close. It kind of shows that I can use the VNA and the Ecal module fairly well

You can see how close I've managed to measure the capacitance and component Q up to several GHz. It agrees very well with the official data for capacitance and ESR. Anyone with VNA experience will know that this is a decent test result. My data is the red trace data and the wiggly blue traces are from the official ATC data for the cap.

[Bazz4CQJ]

Originally Posted by G0HZU_JMR

I didn't initially comment on this RF voltmeter circuit because it has so many technical issues/flaws that it simply isn't worth building or even simulating.

Sadly, I don't have the expertise to make any comment, but note that both you and Wrangler are not impressed.... and it didn't work well when I built it.

That said, the original article refers to two previous designs which it draws on, so it seems like 3 "designers" have published dubious designs on the web and that's something I'll be taking to heart! For those of us who cannot design their own, it is 'slightly worrying'.

B

[Skywave]

Originally Posted by G0HZU_JMR

Can't you just simulate it on a freebie simulator like SimetrixIntro and you will see that you must be doing something wrong?

I have never heard of that simulator. But then I've only vaguely heard about any such 'simulator' and never used one - and that's because the need has never arisen. It's "never arisen" simply because I don't have the experience nor in-depth knowledge of suchlike, nor the advanced test equipment that you seem to have. In essence, with circuits like this I have always taken an elementary 'suck it and see' methodology. I'm a retired electronics technician with relatively simple test equipment operating from my home, not a professional design engineer with all the sophisticated tools which I would expect to find in a well-equipped professional R&D R.F. design & test laboratory. With R.F circuits like this one, that aforesaid approach of mine has almost exclusively been along these lines:
(a) find a 'proven circuit',
(b) build it as a bread-board (with due regard for the conditions it will / should operate at),
(c) using a signal generator and a 'scope (plus probe) and / or my 'surveillance type' spectrum analyzer, evaluate its performance;
(d) investigate any short-comings in either the stated / implied performance if my needs are not met by that build.
That approach has usually produced satisfactory results, albeit sometimes, eventually.

---------------

Quote: "you will see that you must be doing something wrong".

Well, yes, maybe. But I am not a newcomer to R.F. circuitry and I like to believe that my understanding of such does go a bit beyond the basics, but it is quite clear that my comprehension of such is far less than yours. Finally, might I just add - and with all due respect - that a simulation is just that - a simulation, with the necessary assumptions built in? The creation of the 'real thing' will always diverge from any simulation to a greater or lesser extent, and the performance of the 'real thing' is what finally counts. However, I do appreciate your comments to date, even if some of them, in their technical sense, are somewhat outside of my comprehension.

Al.

[Skywave]

Originally Posted by Bazz4CQJ

Perhaps you could add 'pragmatism' to your toolbox - I think it's a virtue.

Point taken, Bazz. For me, in almost everything that fires my imagination but which reveals a hole in my understandings, I'm motivated to ask "Why?" In that sense, I'm my own worst enemy!
But in another sense, you're right. This task has taken up a disproportional amount of my time: it's almost become an obsession - which is not good, by any metric. And it's starting to become a bit of a chore, too .

Al.

[G0HZU_JMR]

, might I just add - and with all due respect - that a simulation is just that - a simulation, with the necessary assumptions built in? The creation of the 'real thing' will always diverge from any simulation to a greater or lesser extent, and the performance of the 'real thing' is what finally counts.

True, but we are only talking about VHF here and circuit simulation can be very reliable up to many GHz in my experience. Obviously, the computer model for the JFET will usually have different Vpo and Idss (etc etc) to a randomly picked JFET from a parts bag but I think stuff like this can be worked around.

I measured the real circuit another way if this helps. Many years ago I designed and built a precision noise source that is 'very' flat from about 200kHz to 180MHz and in the image below you can see I have fed it into my HP8566B analyser on 1dB/div and stored the trace (the top trace).
The trace below it is what happens if I put the buffer circuit inline. It shows a drop in level of about 0.7-0.8dB just like the VNA. But it looks flat if you look at the difference between the two traces. Note that I've used precision 10dB attenuators to improve the less than perfect source and load impedance of the noise source and the HP8566B. This helps minimise any mismatch uncertainty here that would otherwise spoil the measurements.

The little 0.4dB blip at 20MHz in both traces is the less than perfect response of the analyser rather than the noise source. This particular HP8566B has an awesomely flat response from 30MHz right up to 2GHz on range 1 but it has the little 0.4dB blip at 20MHz that spoils the perfection. The sharp rolloff in response above 180MHz in both plots is due to a sharp band limiting lowpass filter inside the noise source.

I'm wondering if your circuit is still operating way up into the negative resistance region. Have you tried reducing the 2M2 to something like 1.5Meg and maybe tried playing with the supply voltage as well to get it flat?

[G0HZU_JMR]

To show everyone what can go wrong, my noise source has a VSWR of about 1.22:1 up at VHF (eg 100MHz) if I remove the final attenuator from it so it doesn't have a decent 50R source impedance. When it is like this the final stage of the noise source is just a 50R MMIC amp feeding a 5dB attenuator. I normally have another attenuator after this to define/improve the source match.

If I then repeat the noise source test using decent 50R cables about a metre or so long (branded cables from a decent maker eg HP) and I also don't use the external 10dB attenuators I get the plot below. The top trace is with the buffer out of circuit and both cable joined together. It looks nice and flat again but there is a trap looming for the unwary...

Because the noise source VSWR is about 1.22:1 up towards 100MHz and the analyser will probably be <1.15:1 here the test system will corrupt the measurement. The setup now is noise source >> cable >> buffer >> cable >> HP8566B analyser with 10dB attenuation internally.

See the plot below. Because the buffer is high Z at the input I can predict the mismatch ripple to be about 20*log(1.22) = 1.7dB of uncertainty (pkpk) just in the input cable. There could also be some uncertainty in the output because the buffer isn't a 50R source. But the HP8566B does have a very good VSWR on range 1 with 10dB or 20dB attenuation selected. So the input uncertainty will dominate.

So you can see just how easy it is to make a seriously duff measurement even when fairly decent test gear is used. The initial 'thru' test looks fine because the noise source is seeing a fairly decent 50R load at the analyser via the two 1m long cables. But it all goes pear shaped when the buffer is put in line. This shows how easy it is to get confusing test results. If I'd used a slightly shorter cable on the input I'd have got a false 1.8dB droop by 100MHz in my test results for the buffer. This is why I mentioned earlier that this particular buffer circuit with its high Z input can be very unforgiving of the test procedures adopted.

[Bazz4CQJ]

Elsewhere on the Forum, Augustinetez has suggested that the AD8307 is a device worthy of attention and a quick search revealed this wideband RF power meter design, originally from those fine fellows at QST....which may be of interest For a few pounds, you can buy something similar online from China!

B

[G0HZU_JMR]

Back in the 1990s when the AD8307 was first released I made a little power head using this chip. This was probably made from a salvaged pre production sample of the AD8307 but I still have it here today and I could post up the performance it offers if that helps? I went for small size and ultra low input VSWR (to minimise mismatch uncertainty) so my power head has a precision (compensated) attenuator at the input to really get the VSWR low across 0-200MHz. It was designed for flat operation to 145MHz and then I use a lookup correction table above this.
I dug it out and measured the input return loss to 200MHz and it is up near 40dB. The VSWR measures less than 1.025:1 all the way up to 145MHz.

It looks really ugly inside as I built it very quickly in a makeshift Teko box. I haven't used it for many years as it was really just a stop gap experiment at the time. I already had an old HP431C power meter with the HP478A head but this only works down to about 10MHz and the little AD8307 power head was a useful alternative until I bought another lab power meter that could go down to 100kHz.

The AD8307 does have a few issues when used as a power meter as it is just a log amp after all. You have to be wary of harmonics, especially odd order harmonics as these can upset the overall measurement uncertainty a LOT. Harmonics at -30dBc can sometimes upset it much more than you might realise. There are modern 'true rms' alternatives from Analog Devices that use a square law detector that might suit some users better.

[Skywave]

Originally Posted by G0HZU_JMR

Have you tried reducing the 2M2 to something like 1.5Meg?

In my post #59, I have stated that I have tried that - but to no avail.

Originally Posted by G0HZU_JMR

Have you tried playing with the supply voltage to get it flat?

Since you wrote that post, yes, I have, but to no avail.

I think it's time for me to draw a line under this - and stop. In my hands, this cct. has proven adequate to meet my anticipated need up to circa. 50 MHz.: that, for me, is sufficient for further development of the overall project concept. This entire thread was simply one of seeking advice as to how to extend the 'flat' B/W as far as possible: no particular limit was required. Should the cct. in this thread become a feature of a successfully completed project, I will report accordingly in this forum.

So it's time to say "Thank you" to all who have so constructively contributed to this thread. Hopefully, what has been discovered will also be of use to other members. Finally, I would like to request that this thread remains open for a little longer just in case any other members wish to contribute to it further.
And again, my thanks to everyone.

Al. / Skywave / Nov. 14, 2016 //

[Bazz4CQJ]

While I'm sorry that your project is proving difficult, Al, I think this has been one of the most interesting threads there has been on the forum in some time and I will be taking some useful lessons away from it.

B

[G0HZU_JMR]

I hope my input has been of some use but it's a shame this hasn't resulted in any improvement in frequency response. To show you why I'm confused about this I played with the simulation and the component models and it showed that I should be able to get it to show a slightly positive slope all the way to 500MHz with a 2N4416A and a BFR91.

So I shortened a few connections and see below for a VNA plot to 500MHz and a spectrum analyser plot to 500MHz.

The VNA plot is calibrated for a full 2 port calibration at -20dBm using an Ecal module and the reference plane is just at the exit point of the PCB launcher connectors. i.e. the SMA solder pin. You can see it has a fraction of a dB positive slope by 500MHz.

To show this reliably on the HP8566B is a bit harder. This is a fabulous spectrum analyser in terms of flatness (above 30MHz) but I've had to use some exotic gear to maintain a good result using just a simple look through test without any normalisation tricks etc. My signal source is an ESGD sig gen with the snazzy electronic attenuator that delivers amazingly flat response. See the image below for the typical flatness to 4GHz for this model of sig gen.

I've then used a couple of high spec Gore microwave cables that would have cost over £1000 each when new and also a couple of new £££ Suhner 10dB attenuators (the best of their 18GHz ones in terms of spec?)

See below for the response on the HP8566B. The top trace is the thru check without the buffer and the lower trace is with the buffer inline. This test doesn't have the integrity of the VNA test but it is a 'simple' test using ultra low loss ultra low VSWR cables and some decent attenuators to manage any mismatch uncertainty. You can see that the analyser plot looks fairly similar to the VNA. The signal looks low on the analyser at -30dBm because I've used the flattest setting of the sig gen (approx -10dBm) and there are two 10dB attenuators inline. So the test is done at a low signal level with no normalisation. I've done it this way to keep it simple and what you see is the raw combined result for the flatness of 'everything' in the system in the top trace and the bottom trace on the HP8566B includes the buffer.

I'll take a couple of pictures of my circuit and then maybe see if I can degrade the performance by slackening the layout and maybe use some different 100nF caps.

[G0HZU_JMR]

The other interesting thing to note is that by 500MHz there should be a strong passive leakage path through the whole circuit through the JFET and the bootstrapping cap in the drain of the JFET to the output. So even with the circuit turned off it should leak a significant level through the passive circuit to the output. Maybe less than 3dB loss at 500MHz with the circuit turned off in a 50R system? It will depend on how much series stray inductance is in the components used in the layout. The series inductance and the leakage capacitance through the JFET will form a path through the circuit and they can complement each other to reduce the net loss through the overall (passive) circuit.

[Skywave]

Originally Posted by G0HZU_JMR

I hope my input has been of some use but it's a shame this hasn't resulted in any improvement in frequency response.

It has indeed been of use - for which thank you. Having said that, I wish I had some of the exotic test kit that you have - and the knowledge of how to use it.
Have done nothing at all on this project for a few days, since certain house renovations projects have, quite rightly, taken priority.

Al.

[G0HZU_JMR]

I can add a bit more 2N4416 info if this helps. The aim of the exercise below is to show that the 2N4416 can provide 'gain' at 700MHz as the amplifier in a simple oscillator circuit. It also shows how good the simulator/model is for this device. For a bit of fun I did a quick and dirty design of a Hartley osc using the 2N4416 model on the Genesys simulator and I had a look to see how far I could push it up into the UHF region. The plots below are for my first attempt. This is a fairly 'safe' design aiming for 700MHz. The negative resistance analysis is given below for S11 and it looks fairly easy to get it to oscillate up at 700MHz with a very simple circuit. Just the JFET, a resistor and a capacitor and a piece of wire to make an inductor. The first graph is the simulation for the oscillation condition/frequency.

Also given below is the VNA measurement of S11 for the the real circuit. This is slightly damped because I have to include a lossy bias choke at the VNA feed point to maintain the JFET ground return for its bias etc.

But you can see that the VNA predicts oscillation just under 700MHz because that is where there is a 'positive' S11 (above 0dB ) and also +/-180deg phase. This demonstrates that there is negative resistance at the required phase shift and so oscillation can occur here at this frequency. The final plot is the spectrum analyser once the VNA is removed and the tank circuit grounded to allow the oscillator to 'run'.

You can see it oscillates pretty much bang on where the VNA says it will. The level is low at -13dBm because I used an H field probe to remotely sniff the oscillator energy. Also note that I only used 'big' leaded parts to build the oscillator, the resistor and the cap are leaded parts and the 2N4416 is in the classic metal can package with 4 legs. SMD would be cheating here as the aim was to show that it could deliver enough gain at 700MHz to start up and oscillate when ugly built from old school leaded parts on a bit of bare copper PCB

[Skywave]

This thread, after my initial post, has gradually centred around the FET buffer as in my post #25. I am no longer investigating that circuit, since the buffer circuit in the Marconi probe gives a superior H.F. response. Development work on that cct. is featured in the thread "R.F. voltmeter - your thoughts, please", q.v., which for me, is the current 'active thread' on this generic topic.

I do not anticipate my making further contributions to this thread, but do very much appreciate the many useful and relevant comments that others have made to it. Thank you all.

Al.

[Argus25]

Member Scimitar, in a post above, made a reference to the wonderful dual gate RF fet the 40673. Don't overlook this one. Its an oldie but a real goodie.

These work very well in the 70 to 100MHz region and with the dual gate you can use the spare gate for AGC control, or to introduce a local oscillator signal.

To see an actual circuit of one of these, in the front end of a vintage receiver, designed by Heathkit, look at around page 7 of this article:

http://worldphaco.com/uploads/SAVING...dio_Board..pdf

(It also shows how they made an IF amplifier out of a ceramic filter and an MC1350 IC).

[Skywave]

The posts in this thread (which I have no intention of adding to) have effectively become relevant to this thread:

https://www.vintage-radio.net/forum/...d.php?t=131879

On that basis, I suggest that this thread here now be closed.

Al.