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Old 30th Oct 2016, 4:25 pm   #21
G0HZU_JMR
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Default Re: FET selection

Yes, the JFET input capacitance of about 5pF is the killer for the basic J310 buffer. It will be OK (as in flat) with resistive sources up to about 150R. By 500R the droop of several dB will be back by 100MHz.

The poor man's 1GHz active probe looks like it achieves low input capacitance because it uses a crude form of capacitive divider at the input. I'll guess that the input capacitance of the FET is about 2pF but the series cap at the input made from PCB shapes will minimise the input capacitance to a lower level.

I suppose the other way to achieve lower input capacitance is to use a compensated series input resistor to act as a resistive attenuator in sympathy with the shunt resistor across the gate. If a divide by 10 (voltage) is OK for the JFET buffer then it should be possible to get the input capacitance down to about 1.5pF if the probe tip capacitance is included. The bonus here would be the ability to handle signals up to maybe 10Vpkpk at the input. The downside is the /10 attenuation for the voltage at the output. So it won't be so good for small signals in terms of S/N at the probe output.
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Old 31st Oct 2016, 5:10 pm   #22
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Question Re: FET selection

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Originally Posted by G0HZU_JMR View Post
The simplest JFET circuit that would kind of do what you want would be one with the classic J310 device. This will easily give a flat response to 100MHz as a common drain amplifier/buffer.
Hmm: interesting idea; thanks. Sounds eminently suitable. Any chance you could provide a suitable circuit, or a source on the 'Net where I could find same, please?

Al.
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Old 31st Oct 2016, 10:40 pm   #23
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Default Re: FET selection

I've attached the basic circuit below but this will have an input capacitance of 5 or 6pF typically. So you will only get a flat response if you use it to probe circuits with fairly low impedance. eg less than 150R. Also the capacitance can obviously detune some circuits.

I've used the J310 a lot over the years especially in the 1990s and the circuit as drawn should run at about 11mA Id typically and the output impedance will be 1/Gm in parallel with 180R so this will be 50R - 60R typically. It won't act as a unity gain buffer though. You will typically see about a third of the voltage at the output compared to what you see at the input. I'm not sure this very simple circuit will do what you want but I've linked to it below. The difference this JFET offers over the others is higher Gm so you get an output Z closer to 50R and also the output level will be higher. But otherwise I'd expect other common JFETs to give a fairly flat response here too.

Have you tried playing with a bootstrapped 2N4416A + BJT to get low input capacitance and flat response? There are some classic circuits available for this but I don't know if they will work with a flat response to 100MHz.
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Old 31st Oct 2016, 11:04 pm   #24
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Default Re: FET selection

Take a look at Troubleshooting Analog Circuits by Bob Pease (relevant section available on Google books). There is a very low capacitance follower active probe design in that which I have used successfully. Uses 2n5458's, one as a current source and one as a follower buffered by two emitter followers (NPN+PNP to kill offset). 3dB point is apparently 90MHz but you could push it past that with some newer SOT-23 FETs and careful construction.
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Old 1st Nov 2016, 12:04 pm   #25
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Question Re: FET selection

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Have you tried playing with a bootstrapped 2N4416A + BJT to get low input capacitance and flat response? There are some classic circuits available for this but I don't know if they will work with a flat response to 100MHz.
Thank you for the cct. as in your post #23.

As for the FET + BJT approach, up to now I have focussed on the cct. as below. (This has featured in another, earlier, thread of mine). With careful construction, I was able to get the response flat to about 55 MHz (approx.); at about 70 MHz, the response was approx. -3dB. However, what has puzzled me about this circuit is C2 and C3. With either or both disconnected, there is no change in the freq. response at all. I suspect that it is the capacitance at the gate of the FET which is the predominant limiting factor. When the 2N4416 was replaced by a BF256A, there was no difference. I do believe that this cct. has the potential to meet my need; probably just a matter of identifying the significant freq. response limiting items.

Al.
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Old 2nd Nov 2016, 8:01 pm   #26
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Default Re: FET selection

experimentation with Enhancement power FETs suggests the limitation is Gate-drain and Gate-source capacitances. Using 10 Ohm source it's possible to get significant RF power at 20MHz from devices normally rated for up to 100kHz applications.

The frequency limits of J310 seem to be set by the combination of internal capacitance and external circuit.

Valves are similar, but also have the limitation of transit time, which isn't a limitation on low power semiconductors. The higher frequency transistors (bipolar or FET) tend to be very low operating voltage, as low as 2.5V for some 20GHz devices. Parts for 60GHz are quite cheap, but 400GHz parts are often bare chip, assembled using a stereo microscope.

Regular SMD only needs a decent magnifying lamp.
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Old 2nd Nov 2016, 8:31 pm   #27
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Default Re: FET selection

#25
C2 and C3 may be too large. What is the self resonant frequency? Above this they will act as inductors. Try 100pF?
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Old 2nd Nov 2016, 9:15 pm   #28
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I'm getting some deja vu here because I think the circuit in #25 has been discussed here before. I think the circuit will be highly device (as in JFET) dependent when it comes to setting up the bias resistor(s) for the correct operating point. Any variation here will result in a less than ideal frequency response and even the possibility of generating a negative impedance at the input. My guess is that you would ideally need to either select on test the JFET or maybe you could play with the value of the 2.2Meg resistor (or the supply voltage?) to achieve the correct operating point. But you should be able to get this circuit to look flat up to 100MHz if driven from a 50R source and into a 50R load.

Quote:
However, what has puzzled me about this circuit is C2 and C3. With either or both disconnected, there is no change in the freq. response at all.
I think the removal of C3 will become noticeable at low frequencies if you directly probed a circuit that had extremely high impedance.

C2 is there to bootstrap some of the capacitance of the JFET. I think that if the circuit is set up properly in terms of operating point then you should see a big dip in response at low frequencies if C2 was removed. This is because the drain waveform is no longer clamped to 'follow' the waveform at the BJT emitter. So the circuit will then misbehave. But if the operating point is wrong then you might not see this effect.

However, I think it might be worth describing the test setup. The circuit in #25 can be very unforgiving of the test equipment around it if you want to get a flat response even with a 50R test setup. This is because neither port of circuit #25 is 50R. One is high Z and one is probably 15-25R. You would ideally need to use a signal source and receiver with port impedances very close to 50R (across LF to 100MHz) if you were to just connect to the circuit via a few feet of 50R coax at each port. There is the possibility of significant mismatch uncertainty here that can give the impression that the circuit doesn't have a flat response. This is because the coax can act as a shallow filter if the test gear isn't exactly 50R and the DUT port isn't 50R either and you have a few feet of coax inbetween. You could easily see 3dB variation across LF-100MHz here even if the source VSWR was less than 1.5:1. I think a 1.5:1 (source) VSWR can give about 3.5dB voltage variation at the DUT port if the DUT has a very high input impedance and you use several feet of 50R coax and a source that isn't as close to 50R as you might think it is. A similar scenario applies at the output port that could give a (false) slope in the frequency response if your test receiver isn't very close to the ideal 50R.

Otherwise I can't see why the circuit would fail to give a flattish response to 100MHz unless you have a poor layout, or there are some rogue components in there or you haven't set the operating point of the JFET. Just to repeat, I think the biasing of the circuit in #25 will be quite unforgiving of variations between JFETs in terms of the ideal operating point that delivers flat gain and low capacitance and avoids the negative input impedance scenario.
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Old 3rd Nov 2016, 6:01 pm   #29
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Default Re: FET selection

Jeremy - that you for your reply. A lot to think about, so comprehensive replies are required from me.

First, my set-up. The source is an HP 8640B sig. gen. It is connected to the BNC input of the buffer by a length of 50 Ω coax. about 1 m. long, approx. At the BNC input, there is a BNC 'T' piece which enables me to connect a coaxial 50 Ω load, thus correctly terminating the cable. The load side of the buffer is an Advantek spectrum analyzer which has an input Z of 50 Ω. It is connected to the buffer output BNC by a thick piece of 50 Ω cable - the type that would be used for handling kW of R.F. Its length is approx. 1m.
When I disconnect the input load termination (the co-ax. 50 Ω), the frequency response does not change. The output level is approx. + 6dB, compared to when the load is connected, which is what we would expect of course.

Second: To check the validity of my measuring technique, when I connect the sig. gen. direct to the analyzer using the same co-ax. cables, the response at the analyzer is flat from < 1MHz to > 200 MHz

Third: If, instead of using the spectrum analyzer, I fit a 50 Ω termination to the buffer output and use my Tek 2465 'scope (via a 10:1 probe which has a flat response to 150 MHz) to examine the buffer output, there is a slight improvement in the response of about 10 MHz.

Fourth: Experiments with the biassing of the gate of the F.E.T. When I change the 2 MΩ resistor, say to 1.5M or 2.5M, the response is notably reduced. I've tried several different types of F.E.T., but the resultant response is the always the same. I might just be unlucky in that the cct. may require F.E.T.s with a high gm, whereas the ones I have tried might be just low.

Assuming that I am not asking too much of the circuit as designed, I am rapidly coming to the conclusion that there must be stray reactance in my prototype somewhere that is limiting the freq. response. The question is finding the predominant reactance. Having said that I have built three prototypes and the response of each has always been the same: flat to about 50 ~55 MHz, then quite rapidly rolling off.

Al.
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Old 3rd Nov 2016, 10:01 pm   #30
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Default Re: FET selection

Thanks for clarifying the test setup. The reason I was asking about the test setup is because this particular circuit will be very unforgiving of any mismatch between the source and the Zo of the test cable.

On the input side, if the cable is assumed to be a perfect 50R cable but the source is 55R instead of 50R (sig gen VSWR =1.1:1) then there is the potential for up to +/-0.4dB of ripple if the 1m long cable was fed into the hi Z buffer without a termination at the other end. But it looks like your 8640B has a good 50R source impedance as it passes this test with or without the termination.

On the output side, if I assume the buffer output impedance is 25R resistive (2.0:1 VSWR typical across the whole band) and your analyser input VSWR is 1.4:1 then you could get +/- 0.5dB ripple on top of the true measurement due to the coax cable and the subtle mismatches at either end. But if your analyser VSWR is much better than this (eg with 20dB attenuation selected) then this mismatch ripple will fall to an insignificant amount.

I simulated your circuit using SPICE models for the active parts and even with strays put in for the layout and lead inductance it was still possible to get a flat response to 200MHz using a 2N4416A and a BFS17. I couldn't find a model online for the BFY90 that I could trust. This is because the models available today will be for clones of the older part and there may be differences. But I'm going to assume that the BFY90 would be OK here.
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Old 4th Nov 2016, 1:07 pm   #31
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Arrow Re: FET selection

Thank you for your reply, Jeremy.

And thank you for your SPICE simulation results: very informative.
Right now, my stock of F.E.T.s (all types) is low: time to buy some more, especially 2N4416, and try again.

Although I will persist with this, a point may come where I feel I have exhausted all avenues of investigation. Although I have tried other ccts., none have performed as well as this one under discussion, but obviously there are others to discover and try. And although this goes against my fundamental concept, I may choose to resort to valves to try to meet the requirement!

Nothing else to add for now.

Al.
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Old 4th Nov 2016, 2:53 pm   #32
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Default Re: FET selection

I managed to find a 2N4416 in an old box of parts (not the A version) and I quickly built the circuit using leaded parts with a reasonably tight layout. But it looks quite ugly and could easily be built better. But I went for speed rather than neatness. I don't have any BFY90s here and so I used a BFR91. I have a large bagful of these that must be over 25 years old. I did a lot of UHF VCO design back then and this was one transistor that I used a lot before moving across to SMD.

Anyway... I tested the circuit on my VNA and it was dead flat right up to 200MHz. It agreed very closely with the simulation. The only thing to emphasise is that the operating point is critical in order to get a flat response and also to get the input to look like a low loss capacitor up at RF. Get the operating point wrong one way and it will look like a larger/lossy cap and get it wrong the other way and the capacitance will go down but the circuit will look like a negative impedance up at RF. Get it right and the gain is flat and the capacitance looks flat as well. So the value of the 2.2Meg resistor is critical here.

I suspect that this circuit was only really intended for use down at LF where the bootstrapping could negate the 10M resistor and also get most of the JFET/circuit capacitance bootstrapped away. This would mean that it could be used to probe very high impedance circuits down in the AF region. But it can also give a very flat response up into the VHF region if driven from a fairly low impedance source.

With my VNA setup I can cancel all the mismatch/ripple issues with cabling etc by doing a full 2 port calibration at the ends of the cables (using an Ecal module) and this means I don't have to worry amount mismatch uncertainty when I connect up to the device under test using my test cables. In other words, the test setup creates virtually ideal 50R test ports right at the input to the device under test. i.e. the same as a simulator.
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Old 4th Nov 2016, 3:03 pm   #33
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Default Re: FET selection

Before giving up it may be worth trying the addition of a second emitter follower to isolate the (50 ohm) load from the existing one.

A very crude analysis ignoring capacitive effects...

The BFY90 (at around 5mA) has a typical hfe of 50 and an ft of 1.6GHz.
With a 50 ohm load on the emitter this gives an input resistance of 50 x 50 ohm = 2500 ohm at low frequencies and 50 x 1.6G / 100M = 800 ohm at 100MHz. (Should be a +1 in there for the purists)

The gm of the 2N4416 (at around 500uA) is 1.5 mA/V so the output impedance of the FET will be 1/1.5m = 667 ohm.

Thus the voltage gain of the FET stage will be 2500/(2500+667) ~ 0.8 at low frequencies and 800/(800+667) ~ 0.55 at 100MHz. a drop of 3dB.

Adding a buffer stage will increase the load resistance seen by the original two stages, thus reducing this effect as well as making the bootstrapping more effective.

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Old 4th Nov 2016, 4:31 pm   #34
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Default Re: FET selection

That might account for some of the droop with the loading from the BFY90, but I think you have to be wary when doing a (very) basic analysis of this circuit. The bootstrapping introduces complexity. Also, the JFET operates with all three device pins at a very similar operating voltage because of the 10k resistors. So this isn't a JFET operating under the usual saturation conditions. Even the self capacitance of the 10k resistors can affect the response up towards VHF.

The bootstrapping to the drain from the BJT will force a waveform that is in anti phase to what you would normally see here. So this is a bit like an input and you can get negative impedance effects at the JFET input up at RF frequencies due to this bootstrapping if you alter the operating point of the circuit.

I suppose you could try comparing the BFY90 against a BFR91 with its higher Ft? I don't have any BFY90s here so I can't do this test.

I really do think that this circuit will work quite elegantly down at AF where the input impedance will be extremely high and the capacitance will be very low (less than 0.5pF?). But up at RF I think the circuit will start to behave a bit differently. But if you bias the circuit at the relevant sweetspot that avoids a negative impedance at the input you can get a very flat frequency response even up towards UHF. But the input capacitance will be more like 2pF up at RF and the parallel resistance will be much lower too. This is demonstrated in the simulation and also when measured on a real circuit using a VNA.
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Old 4th Nov 2016, 5:03 pm   #35
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Default Re: FET selection

I don't have a BFY90 here and I'm using a BFR91 and this has a typical Ft of 3500MHz at a few mA Ic.

So I extended the range of the simulation and the simulation predicts the 2N4416 + BFR91 buffer will droop by just 0.5dB by 500MHz in a 50R test jig. This simulation includes the package/lead inductance for the caps, resistors and transistors and layout strays of my crude layout. Also, the simulation relies on me setting the operating point of the circuit such that any negative impedance at the input is (just) avoided.

When I measure the real circuit on the VNA (using the 2N4416 and the BFR91) and set the operating point as above the droop by 500MHz measures about 0.5dB. So it agrees again

Have you checked to see if your BFY90 is a real one and not a low performance clone marked up as a BFY90? It's a real shame I can't find one here. I've probably got one in the loft in an old Pye Pocketphone (Not sure, did they use a BFY90/91?) but it would take a lot of rummaging to find one.
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Old 4th Nov 2016, 7:43 pm   #36
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Quote:
Adding a buffer stage will increase the load resistance seen by the original two stages, thus reducing this effect as well as making the bootstrapping more effective.
An additional issue with the 50R external load resistance is that the linearity won't be very good into an external 50R load with the output BJT biased at just 5mA. I think it would be quite poor here unless the circuit was changed. Maybe by adding the extra stage you suggested.

The old Marconi TK2374 RF probe I have here doesn't use bootstrapping at the JFET but it does use a JFET followed by an emitter follower (with 200R back across B-E) followed by a low gain common emitter stage. So it uses three stages rather than just two. This final stage allows the probe to be adjusted for unity gain overall when probing 50R circuits and it has a 51R resistor in the collector of the transistor to allow it to interface to a 50R cable to the analyser. The collector current is fairly modest but it still achieves reasonable linearity with a two tone test
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Old 4th Nov 2016, 9:20 pm   #37
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Default Re: FET selection

I dug out the schematic for my old Marconi TK2374 >100MHz RF probe here and I've posted up part of the schematic below. I had a quick go at simulating this and one or two things may be of interest. The circuit uses a supply voltage of about -7.5V after being shunt regulated down from -15V.

The 200R strap across the B-E of TR2 helps with the input impedance but it does appear to come at a price. Without the series 100R resistor at the input the probe generates a negative resistance at the input at frequencies above about 25MHz according to the simulation. This negative resistance reaches about -40R at 100MHz and it stays at -40R all the way to 200MHz. So I think that one reason this probe has a series 100R resistor at the input is to keep the real part of the impedance looking positive across the whole frequency range. -40R + 100R = 60R. So it looks like a tiny capacitor in series with a resistance of up to about 50R

This really is a nice old circuit and worthy of consideration for anyone wanting to make a basic RF probe for an analyser up to about 200MHz. It looks like the designer was able to measure/predict the input impedance would go negative up at VHF and that's probably why the 100R resistor is there. It may also help with overload protection I guess.

After seeing this on the simulator I measured the probe input on my VNA and the capacitance was at about 6pF and the real part of the impedance Rs was typically 40R. This is fairly close to the simulation. So without the 100R series resistor in the tip the probe would have an undesirable negative resistance. I think the probe barrel adds a fair bit of capacitance at the tip and my probe doesn't have the original E300 JFET in it. The spec for tip capacitance is about 5pF and I think mine is slightly higher because it has a J310 FET in place of the E300. But that's just a guess.

The other thing to note is that the simulated noise figure for this probe is much lower than the simulated noise figure of the bootstrap circuit that is the subject of this thread. The little Marconi probe really does look to be a nice circuit
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Old 4th Nov 2016, 9:42 pm   #38
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Default Re: FET selection

I'm following this thread with great interest, though some of the discussion is "stretching" my amateur expertise . I started building an RF voltmeter a while ago, but ran in to problems with the FET buffer amp, and the project went in to the "Pending Tray".

Do you know what the transistors are in the Marconi probe Jeremy?


Thanks

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Old 4th Nov 2016, 9:48 pm   #39
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Default Re: FET selection

I just checked and the BJTs, TR2 and TR3 are BFY90s!

The JFET should be an E300. Not sure how available these are but mine works nearly as well with a J310 and a minor tweak to the operating point with R12.

Looking in the manual the Ic for the final amplifier is supposed to be set to about 21mA as the setup requirement for R12 is for 1.1V across the 51R collector resistor of TR3. So the linearity should be quite good compared to the bootstrap buffer discussed in the thread if it is terminated in 50R.
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Old 4th Nov 2016, 10:57 pm   #40
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Arrow Re: FET selection

Thanks for all your replies, gentlemen: things are now getting really interesting.

Just a quickie from me for now. I found the Marconi probe cct. on the 'Net just few days ago: it is now in my list of ccts. to try. Incidentally, on the 'Net, one datasheet for the E300 F.E.T. stated that the E300 can be replaced by a BF256A.

Jeremy: you asked "Have you checked to see if your BFY90 is a real one and not a low performance clone marked up as a BFY90?"
No, I haven't - and moreover, I'm not sure how I would discriminate between the two. But quite some time ago I did try a b/band amp. that used 3 BFY90 which I had built many years ago and had carefully recorded its performance - which was quite impressive. However, when I recently built it again - using the BFY90 that I have now, the HF response was very disappointing. Time to add 'BFY90' to my shopping list!

Al.

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