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Television Standards Converters, Modulators etc Standards converters, modulators anything else for providing signals to vintage televisions.

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Old 5th Apr 2011, 11:39 am   #61
pitbuell94
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Default Re: 819 line standards convertor.

Hi Dears All,

Please find in attached file, the main functions used in my design.

Hope this would help someone.

Frédéric Cabanes.
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Old 5th Apr 2011, 2:01 pm   #62
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Default Re: 819 line standards convertor.

Hi,

Small information concerning my previous post.

The main clock frequency is 50 MHz.

About unit 625:

This unit allows normal function concerning the TDA8708A in mode 2.

It supply signals SEL TDA8708, WR_CLK, GATE A and GATE B to the TDA8708A.

GATE A and GATE B are complement of signal Hsync and Burst Blanking coming from LM1881.
These signals allows the TDA8708 to run in mode 2 => see data-sheet.

WR_CLK are sample frequency for actually in my design 512 dots per line.

SEL TDA8708 is signal to select the right video input when necessary.

It supply also signals START_819_INT, RST_ FIFO_INT, VIDON_625_INT, WR_CLK_INT

START_819_INT allows to start the read process.
RST_FIFO_INT : reset the FIFO pointer at each field.
VIDON_625_INT : allow the write operation concerning FIFOs.
WR_CLK_INT: this is the write clock for 512 pixel per line.


About unit 819.

FIFO1_RD_EN and FIFO2_RD_EN, RD_CLK_INT, VIDON_819, SYNC_int, RD_CLK_EXT, START_819_INT.


FIFO1_RD_EN and FIFO2_RD_EN are signals driving the FIFO 1 and 2.
By correct driving, you have 4 lines in place of 3.

RD_CLK_INT: this is the frequency reading signal for 819 operation.

VIDON_819 : this one allows the interpolator to supply the correct data depending to available video signal or not.

SYNC_INT: this is the complete synchro for horizontal and vertical information.

RD_CLK_EXT:this is the frequency reading signal for 819 operation concerning TDA8702 operations

START_819_INT:this signal comes from 625 unit. it drive the 819 unit to start the read process.

UNIT FIFO 1 and 2:

This unit is drived by unit 625 and 819.
it supply a video signal without any synchro signal.

Output of this unit go true to the interpolator.

unit INTERPOLATOR:

By mixing the signal coming from unit 819 and FIFOs, the interpolator add to the video signal coming from the FIFOs the SYNCHRO signal.

When VIDON is off and SYNC_INT is off, the signal VIDEO819 => black level or 0100 0000.

When VIDON is ON, signal VIDEO819 is the value of FIFO1 (and/or) FIFO2.

When SYNC_INT is ON, the value of VIDEO_819 is sync level or 0000 0000.

Have a good day.

Frédéric Cabanes.
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Old 5th Apr 2011, 3:02 pm   #63
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Default Re: 819 line standards convertor.

Hi Pitbuell94,

It would help me, if you could add the hole schematic.
I have about 15 TV sets working with 819 lignes, and it could help me,
not to change all to 625 lignes.

Best regards,

The German Dalek
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Old 5th Apr 2011, 3:57 pm   #64
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Default Re: 819 line standards convertor.

Hi Dear Sir,

The schematic is actually under process.

I have some problem to manage all my differents VHDL design in a single design.

All VHDL entities work OK it-self but not together .

All electronics parts work well on test board.

I hope quickly I found the solution to mix all my VHDL entities together.

Frédéric Cabanes.
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Old 6th Apr 2011, 4:28 pm   #65
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Default Re: 819 line standards convertor.

Hi,

For those who have some interest of it, I give the VHDL code of my design.

I'm sure it's possible to improve this code because this is my first try.

Code of the last fifo follow in the other post.

It's the same code of fifo1.

Have a good day.

Frédéric Cabanes.
Attached Files
File Type: txt top_module_convertisseur_819.txt (5.6 KB, 100 views)
File Type: txt driver_625.txt (6.6 KB, 101 views)
File Type: txt driver_819.txt (5.4 KB, 91 views)
File Type: txt fifo1.txt (2.3 KB, 78 views)
File Type: txt interpolateur.txt (1.2 KB, 74 views)

Last edited by pitbuell94; 6th Apr 2011 at 4:39 pm. Reason: finger go too fast ...
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Old 6th Apr 2011, 4:29 pm   #66
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Default Re: 819 line standards convertor.

Hi,

The last code of fifo2.

Frédéric Cabanes.
Attached Files
File Type: txt fifo2.txt (2.3 KB, 87 views)
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Old 7th Apr 2011, 2:37 pm   #67
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Default Re: 819 line standards convertor.

Hi Tubesrule and PPPPenguin,

Can I disturb you concerning stranges things in VHDL?

All my single design work OK into my NEXYS2 board and by ISE simulator.

When I put all them into a single design, 3 of these files show warning > FIFO2, 819 and INTERPOLATOR.

Did you have any idea ?

Thank you very much for your support.

Frédéric Cabanes.
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Old 8th Apr 2011, 1:20 pm   #68
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Default Re: 819 line standards convertor.

Frederic,
Warnings are not necessarily a bad thing. It depends on what they are. On a large project using an XC6SLX100 I may get 200 or so warnings that I ignore. Things like unconnected ports on BRAM will give warnings but may be perfectly correct for your design. You just need to investigate each warning to decide if it will affect you or not.

Darryl
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Old 8th Apr 2011, 1:38 pm   #69
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Default Re: 819 line standards convertor.

Only 200 warnings? I seem to get 1000s, even on a XC3SD1800. Mainly from synthesis. Most of them are unimportant (for example 'unconnected output') so I use the filter capability to hide them. Ones that matter include 'unconnected input'

There are many fewer warnings from translate, map and P&R but they are usually more important.
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Old 8th Apr 2011, 6:34 pm   #70
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Default Re: 819 line standards convertor.

Maybe I was low at 200 I guess that's the amount that are usually important enough to review.

Darryl
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Old 9th Apr 2011, 7:02 pm   #71
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Default Re: 819 line standards convertor.

Hi TubesRule and PPPPenguin,

When I talk about error, I'm talking about synthax error.

The strange behaviour is that when I check synhax about each unit only, the synthax is coorect and the simulation too.

When I check again the synthax of my complet design, synthax of FIFO and modul 819 appears with a red cross.

The design 625, FIFO2 and INTERPOLATOR are with GREEN label.

All the design with RED CROSS have a good simulation.

I have in fact no warning at all.

Any idea?

I get crazy

Tonight, I get with saturday night feever

Thank you for your help.

Frédéric Cabanes.
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Old 9th Apr 2011, 7:09 pm   #72
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Default Re: 819 line standards convertor.

Hi,

In attachede document, the screen shot of the bahaviour.

Frederic Cabanes.
Attached Files
File Type: doc Wrong synthax with complet design.doc (510.5 KB, 89 views)
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Old 11th Apr 2011, 1:09 pm   #73
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Default Re: 819 line standards convertor.

Frederic,
What errors are you getting.
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Old 11th Apr 2011, 2:16 pm   #74
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Default Re: 819 line standards convertor.

Hi Darryl,

On the screen shot of my previous post, you can see for each control of synthax of each entites a result with a red cross or green mark on the left side.

In attached file, this is the screen shot of the synthax checking of the top design.

This checking is OK with a green mark on left side.

I don't understand what is wrong.

Maybee a big error from a newbee ...

Thank you for your help.

Frédéric.
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File Type: doc synthax with no warning of top design.doc (133.5 KB, 78 views)
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Old 11th Apr 2011, 2:35 pm   #75
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Default Re: 819 line standards convertor.

We need to see the synthesis report file (projectname.SYR) or the synthesis messages screen (see attached image) . Preferably both of these.
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Old 11th Apr 2011, 3:00 pm   #76
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Default Re: 819 line standards convertor.

Hi PPPPenguin,

A screen shot of my design.

Thank you very much.

Frédéric.
Attached Files
File Type: doc Synthetise_XST_ 819_lines_converter.doc (138.0 KB, 78 views)
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Old 11th Apr 2011, 3:03 pm   #77
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Default Re: 819 line standards convertor.

1. It would be more useful to have the .SYR file. Then we can see the full text for each warning.

2. I note that the "filtered" box is ticked. This means that some messages may not be shown.

3. There are no errors shown.
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Old 11th Apr 2011, 3:16 pm   #78
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Default Re: 819 line standards convertor.

Hi,

Please find the missing SYR.

Thank you.

Frederic.
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File Type: doc SYR file _concerter_819.doc (114.5 KB, 101 views)
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Old 11th Apr 2011, 3:39 pm   #79
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Default Re: 819 line standards convertor.

You said you had some errors. There are no errors shown for this synthesis.
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Old 11th Apr 2011, 3:52 pm   #80
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Default Re: 819 line standards convertor.

Hi,

Something is very strange because I had some red cross sometime on the left side.

I 'll make the UCF file and next, I try all the system.

Than you very much for your help.

Can I ask you something concerning my FIFO design?

I want a synchronous read but all the time, with my design, the RAM is made by LUTs and not by block RAM.

I put the read into a process but all the time, I have an info of RAM are done by LUTs.

Maybe is not important but I don't know.

Frédéric.
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