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Television Standards Converters, Modulators etc Standards converters, modulators anything else for providing signals to vintage televisions.

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Old 7th Jan 2011, 2:44 pm   #41
tubesrule
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Default Re: 819 line standards convertor.

Designing Full and Empty logic within two clock domains is not trivial, especially if no other parameters are know. If for instance one the the clocks or clock enables is known to be much slower than the other, a "valid" signal can be generated to tell the higher speed clock when it's safe to read the slower address counter since you know it won't be changing. Another method is to take multiple readings of the slower address counter with the higher speed clock and compare them to make sure you have a stable reading. This latter approach only works if the higher speed clock is much faster then the lower speed clock (>3X).

As Jeff points out, it is much better to eliminate the need for Full and Empty signals by design. Sometimes this is not possible, but many times data entering and leaving the memory are in known blocks, so this can be used to your advantage. Since you know you will only be moving data into the memory at a fixed rate during an input field, and only be moving data out of the memory at a fixed rate during an output field, this can be used to your advantage. If you guarantee by design that the start of the output field is later than the input field, and there is enough memory so the read and write pointers can never collide, than you have no need for Full and Empty flags.

Keep in mind that this metastability issue is not unique to fpga's but affects all logic design with multiple clocks, and with 16 global clocks available in a typical fpga, it's just easier for this to happen.

Darryl
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Old 7th Jan 2011, 4:33 pm   #42
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Default Re: 819 line standards convertor.

Hi,

In fact, if I design a large FIFO, I should avoid this problem.

So, I think I put 1 or 2 line more in my design.

I try to use CoreGen, but it's not interesting for me because I want to understand what I do, even If I make mistake and if I spent 1 year to do it.

I see with coregen, a black blox is created with all signal.

I assume it's easier.

When I talk about storing line, in fact, I just store data during active video period => 52µs.

I don't store complete line with synchro pulse and the rest.

I'll add all the missing data later just before the TDA 8702.

I try next monday some code with real component on a board : maybee a barbecu is coming soon

Frederic.
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Old 14th Jan 2011, 7:23 pm   #43
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Default Re: 819 line standards convertor.

Hi Darryl and PPPPenguin,

Make this converter seems to be a nightmare .

In fact, the hard part with TDA8708, LM1881 and TDA8702 is not a big issue.

All the part are on a board but nothing run . (nothing burn too ).

The main and the big issue is the software to drive all the function.

Well, I need some information.

When I design my VHDL code, I suppose I build the design of the read part and write part as 2 single separate design part?

Only a signal coming from the write part give the information to the read part that there is some data ready to read.

In my design, after 2 lines comes, I want to start the read part.

Of course, I need to calculate the time needed to have good synchro signal between 819 and 625.

Let me explain my point of view :

Because I start to read 819 signal after 2 lines coming from 625 and because the video signal comes at line 23, I start to read line for 819 signal at the start of line 25.( I need a minimun of 2 lines to start my process...).

So, this time need 64µs * 25 line => 1536 µs.
The VBI for 819 is equal to 38 lines * 48,84 => 1855,92µs.

Then, 1855,92 - 1536 => 319,92 µs.

319, 92 µs / 64 µs => 4, 998 lines

So, the start of field one in 819 starts at the beginning of line 621 of 625 lines standart.

Is-this correct or do I drink too much ?

If I start my read process at line 621, in fact, I loose the first picture coming in the system, but normaly the rest of the process should be well synchronised, isn't it?

Have a good night.

Frederic Cabanes.
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Old 15th Jan 2011, 7:59 pm   #44
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Default Re: 819 line standards convertor.

Hi Frederic,

"When I design my VHDL code, I suppose I build the design of the read part and write part as 2 single separate design part?"

This should be one design but two separate processes. You can break the processes out into modules, but there really is no benefit on a design this small.


"Only a signal coming from the write part give the information to the read part that there is some data ready to read."

As long as you synchronize this to the read clock with at least two FF's, this will be fine.


"Because I start to read 819 signal after 2 lines coming from 625 and because the video signal comes at line 23, I start to read line for 819 signal at the start of line 25.( I need a minimum of 2 lines to start my process...)."

Yes, you need to offset the field on the 819 side from the 625 side by the time it takes you to process an output line, which would be two 625 lines plus any overhead.


"So, the start of field one in 819 starts at the beginning of line 621 of 625 lines standart."

This sounds about correct, but will be dependent on your processing overhead, so may need to be adjusted.

Darryl
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Old 17th Jan 2011, 12:16 pm   #45
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Default Re: 819 line standards convertor.

Hi Darryl and PPPPenguin,

Here I made a simple design of fifo without any flag.

I haven't test-it.

Do you see something strange.

I just put one clock at this moment.

Thank you very much foryour help.

Frédéric.
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File Type: txt simple_fifo_N°3 without flags.vhd.txt (2.8 KB, 96 views)
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Old 17th Jan 2011, 2:31 pm   #46
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Default Re: 819 line standards convertor.

Frederic,
That code looks fine. Of course with only one clock there will not be any meta-stability problems.

There are different ways to look at initialization. What you have done is asynchronous initialization at the beginning of the process. There is nothing wrong with this, but you must ensure that all the signals that comprise the reset state are synchronous to the process clock or you may have meta-stability.

Darryl
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Old 28th Jan 2011, 2:53 pm   #47
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Default Re: 819 line standards convertor.

Hi dear All,

I'm still in progress.

Actually, I've ordered and receive all the spares parts.

I hope(maybee...) my converter will work fine for the meeting with french collegue we 'll made the 13 march close to Paris.

As soon I have brand news, I 'll made a post and photos.

Frederic Cabanes.
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Old 28th Jan 2011, 3:02 pm   #48
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Default Re: 819 line standards convertor.

I am writing an article for the BVWS Bulletin which should be published in May 2011. Here is a quote from my text:

Quote:
Just because an excellent converter is available at a reasonable price that’s no reason for enthusiasts to stop experimenting. A man in France is taking his first steps to generate 819 line signals using FPGA methods.
If you have any worthwhile results, especially photographs, by March I would be interested in including them in my article.
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Old 28th Jan 2011, 3:11 pm   #49
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Default Re: 819 line standards convertor.

Hi Dears Sirs,

This is my last design concerning my FIFO with asynchrone write and read operation.

Hope this 'll run in normal way.

For those we need english translation concerning this code, I can do it.

I'm surrely not the best in VHDL, but I can give some help.

Have a nice week-end.

Frédéric Cabanes.
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File Type: txt fifo_asynchrone_vhdl_bonne_version.txt (2.2 KB, 94 views)
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Old 28th Jan 2011, 3:14 pm   #50
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Default Re: 819 line standards convertor.

Hi PPPPenguin,

Greats thanks concerning your proposal.

I think quickly I'll work hard to finish this and I stop to sleep.

I can give you all the code ( I know this code will not be the best solution ) and the spare parts I use.

Frédéric.
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Old 2nd Feb 2011, 12:32 pm   #51
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Default Re: 819 line standards convertor.

Hi PPPPenguin and Darryl,

I have a question.

What happens in my last FIFO design when the wr-ptr and rd-ptr reach the last position?

I suppose the counter return to 0 or first writtable position, isn't-it? and the same for readpointer?

If this way of thinking is right, I don't need to add to my design a signal to reset WR-ptr and RD-ptr in this way => Read-reset and write-reset.

Then my fifo will run for ever till signal wr-clk and wr-en are on and I just need to take care about signal RD-data, wr-data, wr-clk, rd-clk, rd-en and wr-en.

Of course, I use rst signal to reset everything.

Thank you for your help.

Frédéric.
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Old 2nd Feb 2011, 1:43 pm   #52
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Default Re: 819 line standards convertor.

Frederic,
I believe the ptr's will rollover properly based on the fifo_depth modulus.

Darryl
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Old 2nd Feb 2011, 2:00 pm   #53
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Default Re: 819 line standards convertor.

Hi Darryl,

Thank you for your help.

Have a good day.

Frédéric.
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Old 7th Feb 2011, 12:08 pm   #54
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Default Re: 819 line standards convertor.

Hi Dears All,

Please find below design in VHDL of my 625 lines driver.

You'll find in attached documents,the screen shots of the simulation and the 2 VHDL files needed for the simulation in ISIM simulator.

Maybee my design need some improvment but it run.

If someone have somequestions, I can translate french in english.

Frédéric Cabanes.
Attached Files
File Type: doc screen_shots_625_lines_driver.doc (711.5 KB, 102 views)
File Type: txt test_bench_convertisseur_625_vers_819.txt (2.6 KB, 87 views)
File Type: txt driver_625_lignes.vhd.txt (6.3 KB, 94 views)
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Old 7th Feb 2011, 12:16 pm   #55
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Default Re: 819 line standards convertor.

Hi again,

The signal are in the screen shot as follow:
HSYNC, VIDON, VCS and VSYNC.

HSYNC is the horizontal pulse.

VIDON is information when active video is visible.

VCS is the vertical counter => note that you should add +1 for each line : for eg line 0 in screen shot is in fact line1.

VSYNC is the complet synchro signal.

I'll change this name by VIDEOSYNC because it could be a source of error for external people.

To use my design, just change " *.txt" by "*.vhd"

Have a good day.

Frédéric Cabanes.
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Old 8th Feb 2011, 1:40 pm   #56
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Default Re: 819 line standards convertor.

Hi PPPPenguin and Daryl,

I meet actually a problem concerning simulation of my FIFO.

I'm able to run correctly ISIM in XILINX ISE with all my design but not at all concerning simulation of my FIFO.

In attached document, this is the design of my workbench.

It's not complet=> just clock signal at this moment because nothing run.

I put the same frequency for both clock => RD_clk and WR_clk.

No signal move on the screen.

Do I forget very stupid stimuli

Thank you very much for your help.

Frédéric.
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File Type: txt test_bench_fifo.vhd.txt (2.7 KB, 85 views)
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Old 17th Feb 2011, 9:46 am   #57
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Default Re: 819 line standards convertor.

Hi Darryl and PPPPenguin,

Did you have some information concerning book or something else about workbenches and code for it.

I can't find any information concerning this or very poor quality.

Did you have some sample?

I don't want you give me code for my FIFO.

I want data concerning how to make a test bench.

Thank you very much for your help.

Frédéric.
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Old 18th Feb 2011, 3:28 am   #58
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Default Re: 819 line standards convertor.

Hi Frederic,
I'm not sure I understand what you are looking for. Can you elaborate?

Darryl
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Old 18th Feb 2011, 4:09 pm   #59
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Default Re: 819 line standards convertor.

Hi Darryl,

I'm looking for a training concerning the rules of how to make stimuli for a work bench.

When I try to simulate with XILINX ISIM, my design stop after a short time.

I want to test my fifo design.

Below, it's the stimuli I need for my testbench.

first, I want reset for 100 ns.

Then, I want WR_EN go hight for continuous time=> in the same time, I need that DATA in's value change from 00 to FF.

4 uS after WR_EN is ON, I want that the RD_EN signal go hight.

Normally, if all the signal are ok, I should see in the RD_DATA, the value I put before.=> valu from 00 to FF.

Next time, I 'll send the screen shot of my bad simulation with wrong signal.

Thank you for your help.

Frédéric.

Last edited by pitbuell94; 18th Feb 2011 at 4:22 pm.
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Old 19th Feb 2011, 1:49 pm   #60
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Default Re: 819 line standards convertor.

Hi Frederic,
I understand what you are looking for. Unfortunately I don't know of any good sources for instruction in setting up a simulation test bench. Perhaps Jeff does?

Darryl
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