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Television Standards Converters, Modulators etc Standards converters, modulators anything else for providing signals to vintage televisions.

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Old 5th Dec 2010, 1:18 pm   #1
pitbuell94
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Default 819 line standards convertor.

Hi Dear Ladies and Gentlemen,

It's my first post in your forum and I'm French so, don't be afraid concerning my language.

I'm repairing old tv set from 1950 to 1970 in B&W with Tube.

You can find some of my post in France in FORUM RADIOFIL.

These Tv work at 819 lines.

In this way, I'm actually building a Video generator based with the NEXYS2 FPGA kit.

I've already finished and tested all synchros regarding the exact specification of the 819 French TV signal signal in VHDL language.

Ok, I know, actually my soft only give a black sceen.

If someone have some interest about the VHDL code, I can give it.

My next try is to store an picture in a Flash with these setting => 737 lines and around 1000 dots=> not very funny to test long time a tv with only vertical and horizontal stripe and to check the real quality of these tv.

I've just finish a soft to convert a BMP to a .coe file( coe file is used to flash rom in the a Xilinx Spartan 3E FPGA).

Then, if this run, I'll try to make a real time converter from SECAM 625 line to 819 B&W.

I know AURORA do it but it's just a personnal challenge because I learn C and VHDL from few months.

Concerning SECAM at 819 lines, some tests were done.

It was tested with a flower> a rose but for reason you know probably, they stop everything,> these system need a very large band to transmit the signal.

Hope I don't disturb everybodies.

Have a nide day.

Pitbuell94(Frédéric Cabanes).
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Old 6th Dec 2010, 12:07 am   #2
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Default Re: 819 line standards convertor.

Hi Dears All,

In attached files, there is some screen shot of simulations of this driver.

I forget a line in the code where signal svideo is an OR function between signal HSYNC and VSYNC.

Hope these data will help someone.

To use the VHDL code, just change extension by " .vhd" and it 'll run in XILINX software.

Have a nice night.

Pitbuell94 (Frederic Cabanes).
Attached Files
File Type: doc screen shot simulation mire 819 lignes.doc (314.0 KB, 335 views)
File Type: txt mire_819_lignes_svideo_driver _synchro.txt (5.4 KB, 229 views)
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Old 6th Dec 2010, 9:39 am   #3
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Default Re: 819 line standards convertor.

Bonjour Frédéric et bienvenue au UKVRR.

Thanks for the VHDL and ISE simulation results. I have been using Xilinx FPGAs since 1993, starting with XC3000 series.

This thread may be of interest.
https://www.vintage-radio.net/forum/...ad.php?t=55630

You may also be interested in some articles about standards conversion on my website. If you have any problems understanding the english I will try to help.
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Old 6th Dec 2010, 11:08 am   #4
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Default Re: 819 line standards convertor.

Hi,

Just few informations concerning the previous screen shot.

There is 4 screen shot showing several signal.

HSYNC > this is the horizontal synchro,

VSYNC > this is the vertical synchro,

VIDON > this is the active visible period between back porch and front porch,

SVIDEO > this is the complete video signal with all synchro but without something visible > this is why I tell previously actually I just generate a black screen.

The four screen shot show the four steps during 819 picture.

Screen shot N° 1 => start of visible period at video line N°39 Field one.

Screen shot N° 2 => end of visible period at video line N°406 and end of Field one at line N°409 with half line for interlaced field.

Screen shot N° 3 => start of visible period at video line N°447 Field two.

Screen shot N° 4 => end of visible period at video line N°816 and end of Field two at line N°818=> in fact line 819 because counter starts at line "0".
Line 0 show the vertical synchro pulse.

Pitbuell94( Frédéric Cabanes).
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Old 6th Dec 2010, 11:20 am   #5
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Default Re: 819 line standards convertor.

Bonjour PPPPENGUIN,

Merci beaucoup de votre aide.
Thank you for your help.

Do you speak fluent French?

Have a nice day.

Frédéric cabanes.
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Old 6th Dec 2010, 11:58 am   #6
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Default Re: 819 line standards convertor.

Quote:
Originally Posted by pitbuell94 View Post
Do you speak fluent French?
I only speak a little french but my partner is a french teacher and can help me. But she doesn't understand the technical words. Jerome Halphen from Paris is an engineer and fellow forum member. He is fully bilingual french/english. I'm sure he will help if necessary.

PS: Il y a beaucoup des villes qui s'appellent Fresnes en France. http://en.wikipedia.org/wiki/Fresne In which Fresnes do you live? Peut etre le Centre Penintentiaire?
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Old 6th Dec 2010, 1:19 pm   #7
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Default Re: 819 line standards convertor.

Hi,

You're right concerning your last answer : "Peut-être le centre Pénitenciaire".

I'm living at Fresnes, close to Paris near the jail of Fresnes.

The postal code is 94260.

When I see my second post, I think there is some informations missing.

So, I give now just few informations concerning the previous screen shot.

There is 4 screen shot showing several signals.

HSYNC > this is the horizontal synchro,

VSYNC > this is the vertical synchro,

VIDON > this is the active visible period between back porch and front porch,

SVIDEO > this is the complete video signal with all synchro but without something visible > this is why I tell previously actually I just generate a black screen.

I someone need it, I can add the odd/even signal.

The four screen shot show the four steps during 819 picture.

Screen shot N° 1 => start of visible period at video line N°39 Field one.

Screen shot N° 2 => end of visible period at video line N°406 and end of Field one at line N°409 with half line for interlaced field.

Screen shot N° 3 => start of visible period at video line N°447 Field two.

Screen shot N° 4 => end of visible period at video line N°816 and end of Field two at line N°818=> in fact line 819 because counter starts at line "0".
Line 0 show the vertical synchro pulse.

Pitbuell94( Frédéric Cabanes).
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Old 6th Dec 2010, 6:56 pm   #8
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Default Re: 819 line standards convertor.

Some comments on your VHDL.

There is no need for async reset "raz".

Always use synchronous design where possible. For example:

You wrote:
hsync <= '0' when (hcs < 63) else '1';

A better idea is to put this within a clocked process:
if hcs < 63 then hsync <= '0';
else hsync <= '1';
endif;


You have a clock prescaler (Diviseur de frequence d'horloge). I do not understand why. Is MCLK 50MHz? All Spartan 3 Xilinxes will clock everything at 50MHz with no timing problems.

I have attached part of a recent VHDL design. It is for a multistandard colour black generator. Much of this design is complicated and not relevant to your requirements. The useful part for you is a 625/525 pulse generator. For example lines 402 to 414 generate the mixed sync waveform. The clock is 54MHz for standard definition.
Attached Files
File Type: txt colour_black.txt (41.3 KB, 182 views)
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Old 7th Dec 2010, 8:42 am   #9
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Default Re: 819 line standards convertor.

Hy,

Thank you very much for your design.

In fact, I'm a newbee concerning VHDL.

This driver it's my firt try.

I'll try your idea.

For me, synchronous or async is a little bit hard.

I need more training.

For my real time converter, I'll use some TDA8703 or TDA8708 as CAN, an LM1881 as synchro separator and finally a TDA8702 as CNA.

Actually , I spent time to design FIFO to store data coming from TDA8708 and add them to the next line and make an average.

Maybee, I'll use an otherway like this to avoid time calculation of average.

Value from TDA 8708 is 8 bits.
Average from 2 line is ((luma line1)+(luma line2))/2 but with this way, in case luma line1 is 0000 1111 and luma line2 is 0001 0000, the result is 0001 1111 or 31 in decimal notation => problem is average give 15.5 who is not possible to code in binary so I want to test this solution.

The end CNA should be an 9 BIT CNA and I keep just the result of a simple 8 bits adder.

In case luma1 is 1111 1111 and luma2 are 1111 1111 end value will be 1 1111 1110 and then I don't lose any value.

Normally today, I'll see Jérôme Halphen.

He is living close to me.

Do you want I give him him "Hello" from you.

Thank again for your design and have a nice day.

Frédéric Cabanes(Pitbuell94).
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Old 7th Dec 2010, 10:35 am   #10
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Default Re: 819 line standards convertor.

When you do binary arithmetic you will always accumulate extra bits. As you said, if you add a pair of 8 bit numbers you get a 9 bit result. If you multiply two 8 bit numbers you get a 16 bit result. You have to decide what to do with these excess digits. For example in my colour black design some of the processing is done with 12 bits. Then I simply truncate the 2 LSB before the DAC. There are also various rounding methods.

Please give Jérôme my best wishes.
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Old 7th Dec 2010, 11:13 am   #11
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Default Re: 819 line standards convertor.

Hi,

You're right.

It's a question of video quality.

Because I never done it before, I don't know the result of trunc the less LSB in case of 2 adjacent lines have oposite colour.

I hope if I trunc LSB, this can avoid too the scale effect.

I 'll see Jérôme this noon.

I disturb him at 9 o'clock , he was sleeping...

I wake-up at 6 and make tests drive in Paris by night.

Frédéric Cabanes.
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Old 7th Dec 2010, 3:38 pm   #12
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Default Re: 819 line standards convertor.

Nice work so far Frederic.

I would like to comment on the async design aspect. Like Jeff mentioned, I like to keep my designs as synchronous as possible as this is the way fpga's are designed to work. However most example code I've seen from Xilinx actually does exactly what you have done with an "if" statement used as the outside loop to set things up. Xilinx uses this method on practically ever process they write.

By using the async CLR/PRE of the FF's you may actually save resources since these are available independently of the synchronous portion. For instance if the LUT adjacent to the FF you are trying to clear is already full, than you will force another LUT to be used to preform the clear, whereas the async CLR is free. Here is an example of some code right from Xilinx:

process(clk, rst, ld)
begin
if (rst = '1') then
desc_in_reg <= (others => '0');
elsif (clk'event and clk = '1') then
if (ld = '1') then
desc_in_reg <= nrz(9 downto 1);
end if;
end if;
end process;

Hope I didn't confuse things more

(Say hello to Jerome from me)

Darryl
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Old 7th Dec 2010, 4:18 pm   #13
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Default Re: 819 line standards convertor.

There is an important app note from Xilinx that says very strongly: "Don't use global async reset". It may be useful for simulation but it's a very bad idea for synthesis. I try not to use async logic at all. The only time I deliberately use async reset is in the classic pulse synchroniser that uses 2 flipflops.

-- 1st half of synchroniser
process (INPUT_REQUEST , GRANT) begin
if GRANT = '1' then PRE_REQUEST <= '0';
elsif rising_edge(INPUT_REQUEST ) then
PRE_REQUEST <= '1';
end if;
end if; -- INPUT_REQUEST/GRANT
end process;

process (CKMAIN) begin
if rising_edge(CKMAIN) then
REQUEST <= PRE_REQUEST; -- 2nd half of synchroniser.
end if; -- CKMAIN
end process;
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Old 7th Dec 2010, 7:49 pm   #14
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Default Re: 819 line standards convertor.

Quote:
Originally Posted by ppppenguin View Post
There is an important app note from Xilinx that says very strongly: "Don't use global async reset". It may be useful for simulation but it's a very bad idea for synthesis.
Are they referring to the GSR of the STARTUP Block here? This would be a bad thing to use in the case of a design with multiple asynchronous clocks since you would almost certainly have metastability coming out of reset.

For what ever reason, Xilinx and most of their IP partners love to use the async clr/pre. I just got some code from a third party IP partner of Xilinx's, and beside them doing things like forcing async delays to makeup for clock delays (always a bad thing) every single process starts with an async IF for the clr/pre's. I have done this in specific situations, but also prefer that everything stay synchronous.

Darryl
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Old 7th Dec 2010, 7:53 pm   #15
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Default Re: 819 line standards convertor.

Found the document:
http://www.xilinx.com/support/docume...pers/wp272.pdf

Async delays are very bad practice. They are unreliable and stopping the compiler optimising them out of existence is difficult.
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Old 8th Dec 2010, 12:40 am   #16
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Default Re: 819 line standards convertor.

Quote:
Originally Posted by ppppenguin View Post
Found the document:
http://www.xilinx.com/support/docume...pers/wp272.pdf

Async delays are very bad practice. They are unreliable and stopping the compiler optimising them out of existence is difficult.
The document does verify that global resets are bad from a timing standpoint and will cause metastability, but local resets where the reset signal is synchronous to the process clock can be used, and this is what Xilinx does. With the reset signal synchronous, it will perform properly and will be correctly constrained. (I'm still not advocating doing this)

For a chuckle, download any Xilinx code, like XAPP514 (SD-SDI) and you'll find an async reset in just about every process.

Darryl
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Old 8th Dec 2010, 9:17 am   #17
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Default Re: 819 line standards convertor.

Hi Dears all,

Thank a lot for all these informations.

Sorry for delay concerning my reply.

I was on the road since this week.

Let me sometime to read everything.

For Darryl, no problem, you don't confuse things more.

Let me upload all document and spent time in front of the fire tonight to learn everything.

I try today to show you my last TV in 819 line running with the famous SCRF-819E.

Jérôme shows me all his fantastic collection.

Have a nice day.

Frédéric Cabanes.
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Old 9th Dec 2010, 10:45 am   #18
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Default Re: 819 line standards convertor.

Hi dears all,

Concerning the RAZ in my design, do you suggest that I don't need it?

For the prescaling, I use it because I make some tests on my nexys2 with some led.

I try each function step by step by visual inspection of the status led because when I start to use XILINX ISE, Idon't know how to use the simulator so I count the status of the led... . to be sure my design run

Now, I understand how to use the simulator.

In the same way, I use every day this calculator => TI-30 from Texas instrument.

Right now, I'm going to use the clock at 50MHz from internal crystal.

Then, pixel time will be at 20ns.

I need to change all valu of my counter, this is not a big issue.

I make the change you tell me concerning this :

if hcs < 63 then hsync <= '0';
else hsync <= '1';
endif;

Have a nice day.

Frédéric Cabanes.
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Old 9th Dec 2010, 10:58 am   #19
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Default Re: 819 line standards convertor.

Quote:
Originally Posted by pitbuell94 View Post
if hcs < 63 then hsync <= '0';
else hsync <= '1';
endif;
This can be expressed even more simply as:

hsync <= (hcs>= 63);

hysnc will then be of type boolean instead of std_logic

I'm not 100% certain but I don't think comparisons like (hcs >= 63) will work because hcs is of type std_logic_vector 63 is an integer. SLV constants must be of the form "101010". For example if hcs is a 10 bit SLV 63 would be "0000111111" If you wish to use a decimal number here you could declare hcs as type integer. Alternatively I think that conv_std_logic_vector(63) would work.

Darryl, I'd appreciate it if you could confirm (or contradict) what I've said.

VHDL is difficult for a beginner. There are many constructs that are obscure. Some that seem totally illogical.
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Old 9th Dec 2010, 3:20 pm   #20
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Default Re: 819 line standards convertor.

Mixing types is really up to the VHDL implementation, but never a good thing to do. Comparing a SLV to an Integer may work as expected, may not work as expected or may generate a fault. There are two ways to handle this, the first being what Jeff showed:

hcs >= "0000111111"

Alternatively you can recast the SLV

conv_integer_range(hcs) >= 63

Both of these methods explicitly tell VHDL what your intent is.

Now with that said, the Xilinx tools would actually work with your original implementation mixing the SLV and Integer, but just because it works now, does not guarantee it will work in a future release. I can think of a few issues, like requiring a When Others in a Case statement in the latest releases when it wasn't required years ago, so it's always best to be explicit.

Darryl
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