SC/MP timing and microcode information - Page 7 - UK Vintage Radio Repair and Restoration Discussion Forum

Karen O · 8th Aug 2020, 4:25 pm

On another aspect of SC/MP behaviour, has anyone EVER used a jump instruction that used a displacement from P1, P2 or P3? Is this useful for anything?

dominicbeesley · 8th Aug 2020, 6:13 pm

Thanks for the NENIN pointers - that sounds about right though I'm wondering if NENIN is sampled at a clock edge to restart the cycle or just latched somehow. It being fed straight to the bus buffers sounds plausible and would make sens. I'll have to rig something up to try some really short pulses on NENIN to find out how it is latched or registered.

I was wondering about how calls into other pages are usually done. Is it usually with a XPPC?

I suppose the pointer relative jumps would be a nice way to do a vtable for object oriented code?

Timbucus · 8th Aug 2020, 6:29 pm

Quote:

Originally Posted by Slothie

Quote:

Originally Posted by Karen O

On this thread and the Mk14 VDU thread we were speculating whether the SC/MP NENIN input responds immediately or whether the SC/MP completes its current cycle before relinquishing.

I think I can say with confidence that it relinquishes immediately, probably via asynchronous logic so there's not even a clock delay. I think the SC/MP gets straight off the bus but takes note if it has been knocked back part-way through a cycle. It will try again when the buses subsequently become free again, perhaps multiple times. There must be a point in each memory cycle when the SC/MP deems 'mission accomplished' and ceases retries.

Do people concur with this analysis?

Now my inner sadist wants to stick a 555 on NENIN and see how it copes running a program.....

With a POT you could make a nice Slomo (remember those on the Spectrum) controller by varying the frequency...

Slothie · 8th Aug 2020, 6:57 pm

I'm currently designing a logic simulator that calculates timings so any info on the timing relationship between XOUT and transitions on NADS, NRDS, NWDS etc would help with making a waveform generator for SC/MP processors..... The data sheets are suspiciously vague on this as I believe you noted before.

Mark1960 · 8th Aug 2020, 7:16 pm

Quote:

Originally Posted by Karen O

There must be a point in each memory cycle when the SC/MP deems 'mission accomplished' and ceases retries.

From figure 4 of the datasheet it looks like NENOUT low indicates the cycle has been completed. But there seems to be no specific hold time between NENIN and NENOUT.

circuitryboy · 15th Aug 2020, 5:12 pm

Quote:

Originally Posted by Karen O

On another aspect of SC/MP behaviour, has anyone EVER used a jump instruction that used a displacement from P1, P2 or P3? Is this useful for anything?

Returning to this question:
Yes, you can make a big jump within the current page.
Or, you can jump (NS say 'transfer control') to ANOTHER page.

8th Aug 2020, 4:25 pm	#121
Karen O Rest in Peace Join Date: Jul 2011 Location: Bridgnorth, Shropshire, UK. Posts: 787	Re: SC/MP timing and microcode information On another aspect of SC/MP behaviour, has anyone EVER used a jump instruction that used a displacement from P1, P2 or P3? Is this useful for anything?

8th Aug 2020, 6:13 pm	#122
dominicbeesley Octode Join Date: Nov 2004 Location: Hebden Bridge, West Yorkshire, UK. Posts: 1,885	Re: SC/MP timing and microcode information Thanks for the NENIN pointers - that sounds about right though I'm wondering if NENIN is sampled at a clock edge to restart the cycle or just latched somehow. It being fed straight to the bus buffers sounds plausible and would make sens. I'll have to rig something up to try some really short pulses on NENIN to find out how it is latched or registered. I was wondering about how calls into other pages are usually done. Is it usually with a XPPC? I suppose the pointer relative jumps would be a nice way to do a vtable for object oriented code?

8th Aug 2020, 6:57 pm	#124
Slothie Octode Join Date: Apr 2018 Location: Newbury, Berkshire, UK. Posts: 1,287	Re: SC/MP timing and microcode information I'm currently designing a logic simulator that calculates timings so any info on the timing relationship between XOUT and transitions on NADS, NRDS, NWDS etc would help with making a waveform generator for SC/MP processors..... The data sheets are suspiciously vague on this as I believe you noted before.