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Old 14th Dec 2018, 4:54 pm   #61
Al (astral highway)
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

Nice illustration, Hugo.

I'm aware of the Fourier series and also the additive determination or synthesis, rather, of square waves, using odd harmonics...

It would be interesting to see what highest harmonic is determinable in the suitably clean square wave that I eventually pass for service in gate driving.

I have a pretty basic digital oscilloscope with only 25MHz bandwidth. It does have a Fast Fourier Transforms (FFF) function but I've never investigated that. It'll go on my list of things to investigate.
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Old 14th Dec 2018, 7:18 pm   #62
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

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Originally Posted by Argus25 View Post
Yes, but the over voltage protection is mediated in these power supplies by shutting down the drive (the SG3524) which in case of this failure would be useless. There are no active crowbar circuits on the output capable of clamping the voltage down. This is one reason why I thought it unlikely the circuit could self sustain oscillations in the event of a drive failure. That was the point I was making.
In such a case, an over-voltage monitor would drive an opto-coupler, triggering a beefy thyristor on the primary side, blowing a fuse just downstream of the high-voltage bulk capacitors. It can be done!

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Originally Posted by astral highway View Post
However, note that this whole winding has a DC resistance (estimated) of a fraction of an ohm. It’s a short circuit to DC in the drain of the MOSFET in the circuit.

...

A pulse transformer that would have enough DC resistance (say 15R) to somewhat limit current in the drain of the driver MOSFET would need 100’s of windings of thin wire. It would accordingly be bulky and to be on quite a large former and so its need to give rise to a high resistance to DC would end up giving it far too much magnetising current and leakage inductance, and the core would likely saturate.

Wasting heat seems counterintuitive with this brief. If we’re trying to get the biggest blobs of current flowing in the gate transformer on the side of the power MOSFETs, there’s something discordant about dissipating 15-20W or more in the driver transistor.
Absolutely!

The driver device does need to be 'on' or 'off', if it's passing standing current, that's just a waste. Similarly, the transformer's winding resistances need to be really low - extra resistance just limits the gulps of charging current into the gates of the driven devices, as well as wasting power.

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With your operating frequency is does seem that transistors would be the way to go, specfically an RF capable power transistor.

...

So it seems you would really require large RF capable transistors rather than mosfets, or the driver will be more awkward. I wonder if Kalee20 agrees with that ?
Kalee reckons that trying to charge a gate capacitance of 24nF from 0V to 10V in 100nsec needs a current of I = C x dV/dt = 2.4A, and a frequency capability of around 5MHz (if you imagine 100nsec as a half-period) - broadly in line with Hugo's estimate of 6MHz. That's outside the capability of an old-fashioned transistor, but well within a reasonably modern planar medium-power transistor. Bear in mind that an RF transistor is a well-specified chip in a super-low inductance package, but other than that the actual chip may not be particularly special unless you pay exotic prices. Used as an emitter-follower, I'd honestly think that the Zetex types I mentioned earlier would do - or even a BD131/132 pair.

Totally agree with Hugo that you need to get it working driving nothing at all, then load it with the representative FETs or IGBTs. You could simulate these with little capacitors, maybe starting at 470pF and progressively doubling the value till you get to 24nF.
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Old 14th Dec 2018, 7:39 pm   #63
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

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Originally Posted by kalee20 View Post
Bear in mind that an RF transistor is a well-specified chip in a super-low inductance package, but other than that the actual chip may not be particularly special unless you pay exotic prices.
That's good to know! Thanks!

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Originally Posted by kalee20 View Post
...used as an emitter-follower, I'd honestly think that the Zetex types I mentioned earlier...

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Originally Posted by kalee20 View Post
agree with Hugo that you need to get it working driving nothing at all, then load it with the representative FETs or IGBTs.

You could simulate these with little capacitors, maybe starting at 470pF and progressively doubling the value till you get to 24nF.
Absolutely - that's bang on my methodology already. I got to switching on charging 2 x 7nF gates with no problem, and 1 x 24nF gate before things unravelled (see back to the start of the thread).

[QUOTE=kalee20;1101501,,Kalee reckons that trying to charge a gate capacitance of 24nF from 0V to 10V in 100nsec needs a current of I = C x dV/dt =2.4A [/QUOTE]

True for average current, surely...but peak current is way higher for the big IGBT bricks with the switching time I showed in the photo?

[Cies=24nF.

Qg=4420 nC from the manufacturer's datasheet]

by another method,

IgatePeak= (VgateOn-VgateOff)/R(gate resistor external)+R(gate resistor internal)
Vgate on=24V
Vgate off=-24V

Rgate external= 3r3R
Rgate Internal=0R1


So IPeak=48/3.4=14.1A per device,

or approx 30A altogether!.
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Old 14th Dec 2018, 10:06 pm   #64
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

Zetex was bought out by "Diodes inc." some but not all of those giant-killing ZTX transistors are still made.

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Old 14th Dec 2018, 11:31 pm   #65
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

Quote:
Originally Posted by kalee20 View Post

Totally agree with Hugo that you need to get it working driving nothing at all, then load it with the representative FETs or IGBTs. You could simulate these with little capacitors, maybe starting at 470pF and progressively doubling the value till you get to 24nF.
Al,

One thing that would also help too, but it is not plainly obvious building a switching circuit, is that if you did re-attempt a class A or single ended driver stage, one way to be sure that the collector current (transformer primary current) and the bias (operating point) of the stage is correct, is to operate it in an analog mode with lower signal level sine wave inputs from the test generator. This way you can view the drive voltages as half sine waves before clipping. Then you can adjust the bias so that the operating point is symmetrical for the drive to each output device prior to clipping. This symmetry is masked over of course when it is driven into clipping and square wave mode, which is the way you intend to use it.
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Old 15th Dec 2018, 6:24 pm   #66
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

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Originally Posted by astral highway View Post
True for average current, surely...but peak current is way higher for the big IGBT bricks with the switching time I showed in the photo?

[Cies=24nF.

Qg=4420 nC from the manufacturer's datasheet]

by another method,

IgatePeak= (VgateOn-VgateOff)/R(gate resistor external)+R(gate resistor internal)
Vgate on=24V
Vgate off=-24V

Rgate external= 3r3R
Rgate Internal=0R1


So IPeak=48/3.4=14.1A per device,

or approx 30A altogether!.
There's something wrong here. 24nF charging from -24 to 24V takes 1152nC not 4420nC, irrespective of whether it's done in 50nsec or half an hour.

Once the gate is charged or discharged, no current at all flows. It's just during the transition that a big gulp of current is demanded.

I suspect that the 24nF is only part of the story, and there's significant Cdg (or Miller capacitance), which is why the total gate charge figure is given. Certainly, shifting 4420nC in 100nsec needs a current flow of 4420nC/100nsec = 4.4A. If you want to switch it in 50nsec, you need double that. The presence of series resistors can't change that, but what resistance can do is limit the current, if your drive circuit slews the voltage significantly faster.

Just looking at the figures, though... Why do you want to swing from -24V to +24V? Most MOSFETs are fully specified at 10V, and have maximum gate voltages 20V. Equally, there's nothing to be gained taking the gate negative (although direct drive from a transformer can't avoid doing this). I had assumed a swing of 0 to 10V which is 4.8 times easier than -24 to 24V!
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Old 16th Dec 2018, 12:52 am   #67
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

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Originally Posted by kalee20 View Post
Just looking at the figures, though... Why do you want to swing from -24V to +24V? Most MOSFETs are fully specified at 10V, and have maximum gate voltages 20V. Equally, there's nothing to be gained taking the gate negative (although direct drive from a transformer can't avoid doing this). I had assumed a swing of 0 to 10V which is 4.8 times easier than -24 to 24V!
........of note, that is why in the transformer drive circuit I suggested, the gate- source voltage can only be -0.7V (forward conduction of the zener) and + the zener voltage which is say in the range of 15 to 20V. Which creates the perfect setup for the mosfet gate voltage swings, albeit not wonderfully efficient as there is power loss in the series resistance on half of the cycle for each resistor, but of course, don't forget, you have this anyway if the output devices were BJT's due to the B-E junction conducting and nobody would worry about it in that case and just consider it a necessary requirement of the drive power for the BJT.
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Old 16th Dec 2018, 8:29 am   #68
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

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Originally Posted by kalee20 View Post
There's something wrong here. 24nF charging from -24 to 24V takes 1152nC not 4420nC, irrespective of whether it's done in 50nsec or half an hour.

Once the gate is charged or discharged, no current at all flows. It's just during the transition that a big gulp of current is demanded.
The manufacturer's datasheet Qg will take into account the charge in gate-drain capacitance with an assumed drain voltage swing, which whomps up the Qg figure somewhat, and it may be a worst case number as well.

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Old 17th Dec 2018, 5:17 pm   #69
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

Quote:
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Quote:
Originally Posted by kalee20 View Post
Just looking at the figures, though... Why do you want to swing from -24V to +24V? Most MOSFETs are fully specified at 10V, and have maximum gate voltages 20V. Equally, there's nothing to be gained taking the gate negative (although direct drive from a transformer can't avoid doing this). I had assumed a swing of 0 to 10V which is 4.8 times easier than -24 to 24V!
........of note, that is why in the transformer drive circuit I suggested, the gate- source voltage can only be -0.7V (forward conduction of the zener) and + the zener voltage which is say in the range of 15 to 20V. Which creates the perfect setup for the mosfet gate voltage swings...
The circuit in post #24 does, yes. But 'wasting' power in a resistor via the 0.7V clamping voltage is just as hurting to fast rise-time for the other device as letting the gate voltage of the 'off' device swing negative.

[There could be some merit in keeping gate voltage of an 'off' device negative - it would give added immunity to spurious conduction if some external agency imposed a high positive voltage slew on the drain. But that's really almost another subject!]

The post # 24 circuit does drive the two FETs by completely different mechanisms:

When the driver FET is turned 'on', the 20V supply is snapped across the whole primary. Immediately, therefore, 20V appears across both secondaries. One secondary reverse-biases its Zener via its 240Ω resistor (which therefore dissipates 1.55W). The other charges the FET gate capacitance, which for sake of argument we'll assume is 24nF, till the Zener diode clamps. The time to charge 24nF through 240Ω from zero to 15V is given by: 15 = 24 x (1 - exp(-t/RC)) and with R = 240Ω and C = 24nF we get t = 5.6μsec, so not very fast.

When the driver FET is turned 'off' the primary is effectively open-circuit, so overall there is just a LCR circuit comprising the transformer's magnetising inductance (L), the two gate capacitances (C) and the two series 240Ω resistances (R), slightly complicated by the diodes. The waveform on the gates will then be part of a sine-wave, arrested by the clamping action of the diodes. If the transformer had built-up just a bit of magnetising current by the 'on' time not being very long, then the rise-time on the gates in the other direction could be slow - indeed, full drive may not be attained. If on the other hand, there had been oodles of amps built-up, the drive could be very rapid - but it would need a transformer with high energy storage capabilities (alternatively, a high Vμsec product).

Deriving design equations for the transformer is possible, but it inherently depends on the 'on' and 'off' times so cannot be regarded as a general-purpose driver in the same way as a IC driver can be used from switching periods of microseconds to days. I have used a circuit similar to Hugo's - with no secondary diodes, much smaller series resistances, and with the addition of an energy-recovery winding - at 75kHz, for duty cycle variable from about 20% to a shade under 50%. As a drive circuit, it runs cool and is efficient. But at very low duty cycles, the 'off' switching speed is lousy slow.
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Old 17th Dec 2018, 10:40 pm   #70
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

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Originally Posted by kalee20 View Post

When the driver FET is turned 'off' the primary is effectively open-circuit, so overall there is just a LCR circuit comprising the transformer's magnetising inductance (L), the two gate capacitances (C) and the two series 240Ω resistances (R), slightly complicated by the diodes. The waveform on the gates will then be part of a sine-wave, arrested by the clamping action of the diodes. If the transformer had built-up just a bit of magnetising current by the 'on' time not being very long, then the rise-time on the gates in the other direction could be slow - indeed, full drive may not be attained.
I agree, but when I posted it I did not know the DC axis of the drive waveform which would determine the DC current on the transformer primary, so later I suggested going to a transistor as the driver device and biasing it into class A (as its easier than biasing a mosfet) so the drive to each fet would be perfectly symmetrical. Also with the large input capacity of the mosfets Al has, the resistor values would have to be lower to get reasonably fast switching. Also after that I suggested driving the primary with a bridge to avoid the DC magnetization current. But the transformer secondary circuit with the zeners I suggested would still work just fine, if the proportions were correct.

However, there still would be more power loss than with BJT's though. This is because in the case of a BJT the transformer secondary voltages only needs to be around a few volts to establish a fairly consistent drive current in the series base resistors on each half cycle, so the power loss is lower when a half cycle is shunted by its series resistor and diode represented by the base-emitter junctions.
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Old 19th Dec 2018, 10:54 am   #71
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

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I agree, but when I posted it I did not know the DC axis of the drive waveform which would determine the DC current on the transformer primary, so later I suggested ... biasing it into class A ... so the drive to each fet would be perfectly symmetrical.
Agree - transformer drive with a variable duty cycle needs care, both to obtain satisfactory operation of the transformer, and to define if any DC restoration is necessary on the secondary to get the appropriate levels. Variable duty cycle, symmetric bidirectional push-pull is straightforward. Unidirectional isn't!

Biasing in Class A however is really not the way forward in a switching circuit. When the driver device turns 'off-ish' there is no virtue in having a few milliamps flowing - you are effectively then just biasing the transformer core with DC (which isn't transferred to the secondary), so you might as well move the Class A operating point down by that many milliamps so that when 'off-ish' the current flow reaches zero. And then you realise that 'off-ish' is REALLY the same as a solid 'off'.

And on the opposite half-cycle, there is no virtue when the driver is 'on-ish' having a few volts remaining across the driver. It just wastes power. You might as well reduce the supply voltage to the driver stage by that many volts and have the driver device hard 'on' rather than 'on-ish'. The transformer primary won't notice any difference! Or alternatively, if your supply voltage is fixed, alter the transformer turns ratio to use ALL the voltage: use the design flexibility that a transformer can give you.

The symmetry aspect - if the driver was to operate in class 'A' then the switching 'off' will be no different if the driver is reduced to zero current rather than a standing few milliamps. The switching 'on' WILL be different if the device is operated as a hard switch rather than as a step-change constant current device. But then I'd be thinking, why have a soggy switch-on when a harder switch-on can be achieved?
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Old 31st Dec 2018, 1:39 am   #72
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Default Re: Sipmos MOSFET fails with no gate voltage applied...

Hi Al,
I was looking at an 8 pin IC the AM0026, that drives the clock inputs on the 8080 CPU in my Sol-20 computer, I didn't think it would be much of a power device.

Then I discovered it was the same as a DS0026 and looked up the data sheet. What I saw made me think of you.

This IC has the ability to drive high capacity loads (20nS for a 1000pF load) and swings 20V and has a peak drive current of 1.5A and it interfaces to TTL. It would be good perhaps as a driver for some of the medium power fets leading to the massive output ones you plan to use:

http://images.100y.com.tw/pdf_file/DS0026.pdf
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