Simple memory card player idea

[ppppenguin]

I've not used Altera, only Xilinx, but I'm sure there is a good range of development boards. Simple designs in VHDL (or Verilog if you use that) ought to compile equally on Altera or Xilinx parts. Obviously if you utilise particular design features that are unique to one or the other you will have to modify your code.

There aren't many of us here at UKVRR who have done FPGA work. Darryl and I have both used Xilinx with VHDL. I think Darryl may also have used Altera.

[Kat Manton]

I've ordered some CF-IDE adapters (99p ea. from China) to make life a little easier; even if a mod. or two is needed I'm mostly connecting to a 0.1" header rather than directly to the CF socket.

Call me old-fashioned, but the direction I think I'm heading in is the "405-line slide-projector"; probably using a Z80 to read frames (slowly) from CF into what amounts to dual-port RAM, where it'll be read entirely by hardware (likely to be TTL/CMOS) into a DAC.

Think of something like an EPROM-based test card generator, with a ROMulator in place of the EPROM(s) and a Z80-based CF card reader periodically transferring new stills into it.

Unless someone wants to try to convince me that I really should get into CPLD/FPGA/etc. and I might enjoy it...

Kat

I don't know about the others however I have used Altera FPGAs, you get a huge amount of free software for them. USB programming adaptors (JTAG) can be had from China for a few quid.

Unless someone wants to try to convince me that I really should get into CPLD/FPGA/etc. and I might enjoy it...

Oh you will, sitting a the kitchen table designing and 'building' complicated digital hardware is good fun, Opencores(.org?) have a lot of modules you can put into your design, such as a dram controller.

[Karen O]

I'm using a IDE-CF adapter too, Kat but I've modified mine to conform to the circuit supplied in:

http://www.elektor.com/magazines/200...29.lynkx?tab=4

This drives the CF card in 'eight bit PC mode'. I would prefer my circuit to work with an unmodified adapter, i.e. in 'true IDE mode'. But for the moment my aim is just to get it to work and then see if I can make it work in IDE fashion later.

The main difference is use of the /IORD and /IOWR lines instead of /OE and /WR. If anyone can shed any light on driving IDE mode I would be grateful. If I do change my circuit to working IDE mode then it must be able to use eight bit data.

I've got the PIC to generate a pixel rate read clock - 40nsec high, 120nsec low. I did this by setting a pulse width modulator for one cycle duration! The resolution is the full crystal frequency so I can control the width of the pulses to 40nsec.

The good news is I'm not over-clocking 4MHz parts this time. I'm over-clocking a 20MHz part instead (but only to 25MHz)

I'm now working on PIC code to get the first locations of the CF card displayed on a 625 line monitor. The 6.25MHz pixel clock is inadequate but that doesn't matter - if I can display a stable picture then my approach has hope. If not, well I go on holiday soon so I can forget the humiliation and shame...

[neon indicator]

Why not use a Cheaper and Easier 18F. They go at 48MHz internally via PLL to a wide variety of external crystals.

Now that I've used 18Fs I'd never buy 10F/12F/16F unless I need a smaller DIP package. As well as DIP 18F2550 and 18F4550, I'm using some 18FxxJxx 44 pin and 64 pin parts via DIL adaptor PCBs into breadboard.

I've ditched my JDM programmer in favour of a pickit2 (very cheap) which is blinding fast and is native USB (Windows or Linux). It can do other stuff too.

[Karen O]

I'm rather hoping that CF cards behave like memory chips and obediently cough up bytes on demand. But if they need handshaking and I have to resort to PC-style buffering then I will lose interest. I'll probably crank down the speed by a couple of orders of magnitude and turn the thing into a cassette player!

I am first and foremost a DSP engineer. I hate the 'goes-as-fast-as-it-goes' disease that has gripped electronics. I hate caching (sure it will work great - MOST of the time). And I hate the whole PC thing with emphasis on throughput but with lousy turn-around (so a PC can handle high definition TV but can't address a simple 1kHz control loop application).

Sorry, I had to rant at someone today - someone just suggested I program DSPs in Java!!!!!!

[Karen O]

tubesrule aka Darryl Hock...? Designer of the Aurora?

I am most certainly in the presence of greatness!

I looked into using a DSP to do standards conversion a while ago. The demands are high: filtering to remove the colour sub-carrier requires at least four multiply/accumulates per input pixel. And then the line interpolation will require three multiply/accumulates per output pixel.

It would be quite a DSP to handle that. Your use of an FPGA is almost certainly the better way to go. And of course, those chips that convert analogue video to a standard byte stream deal with the sub-carrier.

In other words, I don't see a better way of doing it!

[neon indicator]

I think FPGA based DSP can easily tdo about 400 Multiply/Accumulate per pixel reasonably cheaply. I use Scilab to to calculate coefficients.

[tubesrule]

Originally Posted by ppppenguin

I've not used Altera, only Xilinx, but I'm sure there is a good range of development boards. Simple designs in VHDL (or Verilog if you use that) ought to compile equally on Altera or Xilinx parts. Obviously if you utilise particular design features that are unique to one or the other you will have to modify your code.

There aren't many of us here at UKVRR who have done FPGA work. Darryl and I have both used Xilinx with VHDL. I think Darryl may also have used Altera.

Just getting back from vacation and playing catch up.

I've also only quoted some projects using Altera and Lattice fpga's that would have benefited from their unique capabilities, but never implemented a design with either. For the most part, Altera and Xilinx compete head to head, and are both good choices.

Originally Posted by Karen O

tubesrule aka Darryl Hock...? Designer of the Aurora?

I am most certainly in the presence of greatness!

I looked into using a DSP to do standards conversion a while ago. The demands are high: filtering to remove the colour sub-carrier requires at least four multiply/accumulates per input pixel. And then the line interpolation will require three multiply/accumulates per output pixel.

It would be quite a DSP to handle that. Your use of an FPGA is almost certainly the better way to go. And of course, those chips that convert analogue video to a standard byte stream deal with the sub-carrier.

In other words, I don't see a better way of doing it!

Since you are versed in DSP programming Karen, vhdl/fpga design would be very familiar to you. This project might be a good excuse for you to get started in vhdl with one of the Xilinx kits

Since all my converters accept standard NTSC/PAL/SECAM inputs, it is much easier to just use an off the shelf video decoder like the TI TVP5150. These parts have excellent chroma filters and provide a simple interleaved Y/C output bus, so you can just ignore the chroma data if desired. The fpga then just does the size and rate conversion, and formats for the output standard.

Darryl

[ppppenguin]

Originally Posted by Karen O

.... filtering to remove the colour sub-carrier requires at least four multiply/accumulates per input pixel. And then the line interpolation will require three multiply/accumulates per output pixel....

Doing decent digital PAL/NTSC decoding isn't trivial. That's why Darryl, myself and most others who need that capability buy specialised chips to do the job. They are now both good and cheap. I know it's possible to do an even better job than these chips but that's a *lot* of work. Conversely, encoding PAL or NTSC is quite easy in an FPGA, as I have illustrated in my recent article in the BVWS Bulletin. I believe Darryl has also done some nice work using an IIR to implement a sound notch in the FPGA ahead of the vision modulator in the Aurora. This would be far too complex as an FIR.

The actual 625>405 conversion algorithms are almost trivial maths. The hard part, if you're taking a DSP or other CPU based approach, is looking after the timings. Real time means exactly that in TV pictures. Apart from the blanking intervals you can't take a break and catch up later. This is why an FPGA approach works so well. It's easy to make counters and all the other miscellaneous logic, all running in parallel, all amply fast enough.

[Karen O]

Well, I've had some success!

The picture on the monitor is being streamed off the CF card without buffering. It is a 200x256 image, stored in the first 100 sectors of the card, and displayed on a 625 line set (non-interlaced) because I don't have a 405 line set yet

A moving image would result if I simply added 100 to the logical block address each frame.

I think this is going to work!

I've reserved the SPI pins of the PIC to add an audio DAC, which I plan to update at 20.5kHz i.e. twice line rate. That will give a respectable 8kHz or so audio bandwidth (what was the original 405 line audio bandwidth?)

I have some artifact issues with my crummy resistor video DAC but other than that, I think I can make an excellent player out of this.

You can just see two ICs under the connecting ribbon - the PIC and the pixel latch.

I tried using an unmodified IDE-CF adapter. It worked except I got two small images side-by-side, suggesting that the card is offering up 16 bit data of which I'm only latching the low byte. I suspect true IDE mode is fixed to sixteen bit transfers...?

Next task: add audio.

[ppppenguin]

Wel done, you've proven the concept.

Originally Posted by Karen O

That will give a respectable 8kHz or so audio bandwidth (what was the original 405 line audio bandwidth?).

Effectively infinite. There is so much space available around the sound carrier that 20kHz bandwidth is trivial. In practice limited by the studio equipment, audio lines to the TX site and the receivers' audio circuits.

[Karen O]

I have my circuit working with an unmodified adapter. It's a matter of issueing a 'Set Features' command to put the interface in 8 bit mode.

You've twisted my arm - I'll see if I can't get the audio to update at 40.5kHz for a 16kHz bandwidth

[neon indicator]

I think in practice 10KHz to 12kHz.

[Karen O]

I'm at the point where I need a 405 line monitor. Where can I obtain such a venerable machine?

Did 405 line TVs ever have A/V sockets on them? Or will I have to build a modulator?

[bluepilot]

An amazing little device, well done! It reminded me of how much things have changed. Back in the 1970s, we needed to add a "large" video memory to our Interdata 70 which had a whole 64kB of memory itself (Our IBM mainframe only had 1MB). We settled for 500kB which took up about two feet of 19" rack space and cost £10000! If only we'd had one of these.

[ppppenguin]

Originally Posted by Karen O

I'm at the point where I need a 405 line monitor. Where can I obtain such a venerable machine?

Did 405 line TVs ever have A/V sockets on them? Or will I have to build a modulator?

I have a couple of the rare monitor version of the Sony TV9/90. I find them very useful. I think that there was also a monitor version of another small Sony 405 set. That's about it for 405 receivers with video input. I also have a Prowest PM14/1A dual standard 14" monitor. This was probably the last 405 monitor ever built and is a very high quality device though not exactly reliable. None of mine are for sale and you're a bit too far away to sensibly borrow one.

Somebody else may have one available. Worth asking in the Wanted section. I don't think it's too difficult to modify an ordinary TV9/90 for video input. There are plenty of these around at moderate prices.

[neon indicator]

A modulator is much easier than what you have done so far.

[Karen O]

Thank you Stuart,

You know, I think the time is not very far away when compression (JPEG, MPEG) will be unnecessary and considered quaint throwbacks (i'm thinking here of when a petobyte memory stick is commonplace).

How things have changed. I remember a student at my uni struggling because he had blown his term's grant on 64kbyte of DRAM!

I sometimes have trouble adjusting to it all.