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#461 |
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Nonode
Join Date: May 2018
Location: Northampton, Northamptonshire, UK.
Posts: 2,593
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I wonder if having DRAM matrix-ed, mean you only had to read all the row addresses to do the refreshing, with the DRAM refreshing all the columns for you? Rather than having to read through the entire memory locations yourself.
Which if CPU had to do this, then it might impact the speed a bit - Maybe more on a 6502 (rather than a microcoded Z80 with more execute cycles per machine cycle), especially if video is accessing the DRAM on the CPU's execute cycle, so not delaying it. Although the video could then effectively refresh the DRAM (In the Beeb, Video Memory was 20K max, but maybe all row addresses of the 32K RAM were accessed?). Although things must have got a bit more complicated with Shadow & Sideways RAM, ensuring all of this was paged-in often enough (However the Master 128 did have quite a few logic arrays to put circuitry in to do this). And with the Z80 in the Spectrum, the ULA no-doubt extended refreshing to the extra 32K DRAM above the base 16K. I imagine things were further involved in the SuperPET, although if Commodore stuck to doing it all themselves, then less of a worry about extending more-limited refresh logic built into CRTC's etc. |
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#462 |
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Octode
Join Date: Mar 2020
Location: Kitchener, Ontario, Canada
Posts: 1,524
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Don’t confuse the number of cycles needed to refresh 64k dram chips and the number of cycles to refresh 64k of dram. Z80 has a 128 cycle refresh counter, which is ok for 4116 type dram, even if the system has 64k of 4116, because all the 4116 dram chips will be refreshed at the same time. The problem starts with 4416, 4464 or 4164 dram which need 256 refresh cycles, so with the z80 the refresh address A7 needs to be toggled for each 128 cycles of the refresh counter. I think the z80 designers didn’t expect memory sizes to increase as quickly as they did, or maybe expected larger dram chips to continue using 128 refresh cycles.
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#463 |
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Dekatron
Join Date: May 2008
Location: Derby, UK.
Posts: 7,966
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Asserting RAS refreshes an entire row of static RAM.
The 6502 accesses memory with every single clock cycle. It puts an address onto the bus as the clock goes high; this takes a few tens of nanoseconds to stabilise, and if the memory is being read, the processor will be expecting data on the bus and stable at the instant the clock goes low again. What the PET does, by means of having multiple copies of the clock signal with precise delays from one another, is:
![]() In the BBC Micro, the memory is clocked at 4MHz, with the processor and CRTC alternately accessing memory effectively at 2MHz each. The CRTC asserts RAS and CAS to read a byte (and refresh the whole row), and then the CPU takes its turn to assert RAS, CAS and read or write a byte. And except in MODE 7, the contents of memory represent not character codes, but individual pixels. So there is actually six-way multiplexing on the DRAM address lines (CPU, CRTC in bitmapped graphics mode with video ULA, and CRTC in Teletext mode with SAA5050; all with variants for the high and low-order bits)!
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If I have seen further than others, it is because I was standing on a pile of failed experiments. |
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#464 | ||
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Nonode
Join Date: May 2018
Location: Northampton, Northamptonshire, UK.
Posts: 2,593
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Quote:
On the lower-front, there was also an old hand-written sticker with the POKE's for changing between Upper & Lower case - See attached pictures. Last edited by ortek_service; 19th May 2025 at 8:59 am. |
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#465 |
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Nonode
Join Date: May 2012
Location: Perth, Scotland
Posts: 2,436
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Thanks all for the DRAM input. I will try to learn a little (that's the best I can promise - old dog, new tricks and all that) from the posts.
74177s turned up today. I put one into the empty UE6 socket and all signals/frequencies are now present and correct on UE6 and UE7 which were absent before - thanks for the pointer Tony. Julie's code now runs with no workspace, stack or zero-page errors (see photo attached). I'm running a soak test now. The next problem is that both PETTESTER and the Commodore Diagnostic clip that I have reckon the PET is only fitted with 16k RAM so I need to work on why that is after thorough testing with ToePost. Colin. |
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#466 |
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Dekatron
Join Date: Jun 2015
Location: Biggin Hill, London, UK.
Posts: 6,034
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When you run a diagnostic program that should access the upper 16K block of RAM, does CAS1/ (UD5, pin 11 as on Sheet 6 of the schematic) ever pulse low?
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#467 | |
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Dekatron
Join Date: Aug 2011
Location: Newcastle, Tyne and Wear, UK.
Posts: 13,694
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Quote:
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#468 | ||
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Nonode
Join Date: May 2012
Location: Perth, Scotland
Posts: 2,436
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I don't have ROM sockets back in yet, but if I boot the Tynemouth ROM/RAM emulator with only ROM being emulated (ie it uses on board memory only), I get 15359 bytes free.
Colin. Quote:
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#469 |
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Nonode
Join Date: May 2012
Location: Perth, Scotland
Posts: 2,436
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I have found this which may be worth pursuing:
http://blog.tynemouthsoftware.co.uk/2015/05/commodore-pet-4032-repair-only-16k.html The Tynemouth diagnostics board gives me lots of High RAM errors right now which chimes with the process he went through. I need to fix the keyboard properly so that I can type some BASIC code as per the link above. Colin. |
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#470 |
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Dekatron
Join Date: Aug 2011
Location: Newcastle, Tyne and Wear, UK.
Posts: 13,694
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In addition to Tony's requested check in #466:-
Did you at any point do the CAS0 / CAS1 signal swapover to switch banks for diagnostic purposes, and if you did (and you swapped the resistors back again) can you just re-check the CAS1 resistor is really soldered? (The resistor, R11, is 'after' the UD5 / pin 11 output). Edit: crossed with your post above, so carry on. |
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#471 |
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Nonode
Join Date: May 2012
Location: Perth, Scotland
Posts: 2,436
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PETTESTER does not go low on UD5/11.
Tynemouth diagnostics gives the attached signals when it is testing high RAM. Colin. |
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#472 | |||
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Dekatron
Join Date: May 2008
Location: Derby, UK.
Posts: 7,966
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Quote:
I had an idea for how to build a "74LS244 in-circuit tester" using just a 74LS86, one transistor and some passives (no 3-input gates), but it now looks as though we won't have to .....Quote:
And we know what a refresh fault looks like, which no doubt will be useful to someone in future.Quote:
What happened under emulation was, the unpopulated memory appeared to work (accesses to the unpopulated memory at addresses &4000-&7FFF probably were affecting corresponding addresses &0000-&3FFF) except addresses ending in &FF always read back as the high-order byte of the address. So, one error in each page tested, and always at addresses ending in FF. If a real PET does that, it could be intentional and if so, might warrant a deeper dive into the schematics and theory of operation. EDIT: This just in! Screenshot of an emulated 4016 (Vice xpet 3.6.1) running the latest ToePost and getting past page &3F, into the unpopulated area. What happened on your real hardware?
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If I have seen further than others, it is because I was standing on a pile of failed experiments. Last edited by julie_m; 19th May 2025 at 8:50 pm. Reason: Picture became available |
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#473 | ||||
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Nonode
Join Date: May 2012
Location: Perth, Scotland
Posts: 2,436
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I'll try it - do you just need the first error screenshotted?
And I had an idea (which I may or may not have mentioned before). Would it be possible to have two rows of the 76543210 characters on the screen - one row for low memory and one for high memory? EDIT: I do have a 3016 with only 16k fitted - I can try the code on that one (assuming it hasn;t brokwn since I last looked at it). Colin. Quote:
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#474 | ||
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Dekatron
Join Date: May 2008
Location: Derby, UK.
Posts: 7,966
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Quote:
Quote:
__________________
If I have seen further than others, it is because I was standing on a pile of failed experiments. |
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#475 | ||
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Nonode
Join Date: May 2018
Location: Northampton, Northamptonshire, UK.
Posts: 2,593
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Well it would seem that PETTESTER isn't accessing the upper 16K for some reason. Are there multiple version of it, for 16K & 32K etc. machines?
Or is it mis-reading the 16K . 32K jumper configuration? It does look-like the Tynemouth diagnostics is actually testing the upper 16K of the whole 32K - which you'd expect wouldn't be too difficult to do, once all of the lower 16K, with zero-page & stack is working OK! And whilst this can be done fairly easily from BASIC (via PEEK & POKE's), any good diagnostic ROM should be able to do this just as well without having to type in small programs, requiring Keyboard all working OK. 6 faulty DRAM IC's does sound quite a lot - I assume you haven't yet changed any in the upper 16K bank? But then quite a few were changed in the Lower 16K - Although not clear yet if all / any of these were actually faulty if the lack of refresh was the real problem, unless you've now re-testing those on a working PET etc. Although that / CAS1 waveform looks a little suspect, as < 2Vp-p and has v.long rise-times / falling-edge isn't that sharp either. However I would suspect 'scope (settings) issues, and I wonder if you still the same if you tried 'scoping / CAS0? Quote:
Last edited by ortek_service; 20th May 2025 at 12:02 am. |
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#476 | |
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Nonode
Join Date: May 2018
Location: Northampton, Northamptonshire, UK.
Posts: 2,593
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Quote:
- Maybe killed by having -6.5V applied to their -5V supply ? (Where he seems he was lucky that more DRAM's weren't damaged / Lower 16K was still functioning with that voltage being so-far out. And unusual to have a 7905 regulator fail like that (Not quite s/c, but not that common for these regulators to go over-voltage) So shouldn't really need to type a BASIC program in, if Tynemouth Test ROM does test this all OK - Although maybe you could temporarily swap the keyboard with your 4032, as presumably easier to do this than take it apart to clean / restore contacts ? If the only difference in connection between the two 16K RAM banks is [O]CAS0/[O] & [O]CAS1/[O], then it does very-much look like multiple (6off) DRAM IC failures in this bank (as well). - Assuming all three voltages supplies measure as expected (On a DMM, at least), so as not to risk further failures. |
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#477 | |||
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Nonode
Join Date: May 2012
Location: Perth, Scotland
Posts: 2,436
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Three error message screens from the 4016 attached fyi.
3016 results to follow. Colin. Quote:
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#478 |
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Nonode
Join Date: May 2012
Location: Perth, Scotland
Posts: 2,436
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That was silly of me. It's not going to work in a 3016 as it's a non-CRTC equipped PET.
Colin. |
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#479 | |
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Nonode
Join Date: May 2012
Location: Perth, Scotland
Posts: 2,436
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PETTESTER works as-is for 8K, 16K and 32K PETs so that's not it.
I'll get the keyboard in a better state first and see where we are with other suggestions. No RAM ICs have been changed in the upper bank yet - I'd quite like to leave it 'broken' in order to carry on testing Julie's code. re CAS0 - see attached with another CAS1 screenshot which looks better. Verdigris on the pins is the claim I'm making for why it's different today, but it's also likely to be operator error. Colin. Quote:
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#480 |
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Dekatron
Join Date: May 2008
Location: Derby, UK.
Posts: 7,966
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There's no reason why it shouldn't work in a non-CRTC PET. The CRTC in the 4000 / 8000 series is just a more general-purpose replacement for a whole bunch of TTL chips in the 3000 series. If nothing is listening on its addresses, the initialisation code will not do anything; but it doesn't have to, because the 3000 series video circuit just does what an already-initialised CRTC would do.
__________________
If I have seen further than others, it is because I was standing on a pile of failed experiments. |
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