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Vintage Computers Any vintage computer systems, calculators, video games etc., but with an emphasis on 1980s and earlier equipment. |
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25th Jan 2022, 11:05 am | #41 | ||
Triode
Join Date: Dec 2021
Location: Michigan, USA
Posts: 40
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Re: The PICL V2 - a development of Karen's 2007 original
Quote:
Quote:
Last edited by Michael - K8LH; 25th Jan 2022 at 11:12 am. |
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25th Jan 2022, 6:36 pm | #42 |
Octode
Join Date: Mar 2020
Location: Kitchener, Ontario, Canada
Posts: 1,265
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Re: The PICL V2 - a development of Karen's 2007 original
I have some of those 32x8 skinny dip rams and also a few 128x8, I thought the fast access time might be usefull.
I think my worst design for assembly pcb was a memory board, 4 off 6264 wide dip on one side with 4 on the opposite side, interleaved with each other to fit within 100mm pcb limit. Also included links for 512x8 but never finished assembling that yet. I used single in line socket strip, soldered alternate sides across the pcb. I was wondering if it might be possible to stack a 68010 in dip64 on top of 2 off wide eeprom for 16 bit data, on top of two off ram in skinny dip. For no reason other than as an amusing assembly. |
28th Jan 2022, 6:21 am | #43 |
Triode
Join Date: Dec 2021
Location: Michigan, USA
Posts: 40
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Re: The PICL V2 - a development of Karen's 2007 original
Question about a potential PICL/NIBL 32K RAM upgrade, if I may?
Basically, if I get a 32K RAM chip working, should I continue to supply 'Page 0' ($0000..$0FFF) from PIC ROM or would there be any advantage copying it into 'Page 0' RAM during startup and running NIBL completely from RAM? PICL code changes and fuzzy forum drawing below (full resolution drawing in ZIP file attachment). TIA... Cheerful regards... Code:
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ; Read RAM macro. Data returned in WREG. ~ ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ; ; new 'RDRAM' macro for 32K RAM on the original Orton PICL ; where RAM /CE line is grounded (and the pull-up resistor ; removed) and RD5, RD6, and RD7 now control the A13, A14, ; and /WE lines while RE2 now controls the /OE line. ; RDRAM macro PHI,PLO ; | movf PLO,W ; address lo (1) | movwf PORTC ; " (1) | movf PHI,W ; address hi + /WE (RD7 pin) (1) | iorlw b'10000000' ; use b'11100000' for 8K RAM (1) | movwf PORTD ; address hi + /WE (hi) (1) | bcf PORTE,2 ; RAM /OE bit lo (on) (1) | nop ; (1) | movf PORTB,W ; WREG = RAM data (1) | bsf PORTE,2 ; RAM /OE bit hi (off) (1) | nop ; extra cycle (1) | nop ; extra cycle (1) | endm ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ; Write RAM macro ~ ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ WRRAM macro PHI,PLO,SCE ; | clrf INDF ; set PORTB (data) to outputs (1) | movf SCE,W ; get data (1) | movwf PORTB ; set data lines (1) | movf PLO,W ; address lo (1) | movwf PORTC ; " (1) | movf PHI,W ; address hi + RAM /WE (RD7) (1) | andlw b'01111111' ; force /WE bit lo (on) (1) | iorlw b'00000000' ; use b'01100000' for 8K RAM (1) | movwf PORTD ; write (1) | iorlw b'10000000' ; force /WE bit hi (off) (1) | movwf PORTD ; complete the write op' (1) | comf INDF,F ; set PORTB (data) to inputs (1) | nop ; extra cycle (1) | nop ; extra cycle (1) | endm Last edited by Michael - K8LH; 28th Jan 2022 at 6:49 am. |
28th Jan 2022, 1:28 pm | #44 |
Octode
Join Date: Apr 2018
Location: Newbury, Berkshire, UK.
Posts: 1,287
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Re: The PICL V2 - a development of Karen's 2007 original
I suppose if you copied NIBL into RAM you could write programs to patch NIBL or replace it with something else! I would imagine reading from the flash would be faster than from RAM, although the SC/MP emulation has delays to keep the cycle timing right so I'm not sure that would make any significant difference.
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28th Jan 2022, 3:44 pm | #45 |
Octode
Join Date: Mar 2020
Location: Kitchener, Ontario, Canada
Posts: 1,265
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Re: The PICL V2 - a development of Karen's 2007 original
It might be best to keep NIBL running from pic rom until after you have the 32k ram working. It will be easier to debug if you separate the changes into smaller steps.
I don’t know if there is any advantage running NIBL from ram. I think I read one of Karen’s notes that the simulation was only cycle accurate from ram, though I think that might have been on the PIC14 and comparing internal rom and ram of the pic. There would be a couple of disadvantages. You lose one 4k page of ram available for user programs and you would need some mapping of the ram pages that might slow the instruction cycles. |
5th Feb 2022, 6:58 pm | #46 |
Triode
Join Date: Dec 2021
Location: Michigan, USA
Posts: 40
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Re: The PICL V2 - a development of Karen's 2007 original
I received PCBs and I'm building up the 1st board while also modifying and testing the PICLV2 firmware for the 16F18877 chip. So far, so good. Stay tuned...
Cheerful regards, Mike |
5th Feb 2022, 8:16 pm | #47 |
Octode
Join Date: Mar 2020
Location: Kitchener, Ontario, Canada
Posts: 1,265
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Re: The PICL V2 - a development of Karen's 2007 original
Looking good so far.
So you didn’t stack the ram, probably best for debug while you are converting the code. The black looks cool, but I find it makes it difficult to find traces if you want to cut and wire mod any links. |
5th Feb 2022, 11:46 pm | #48 | ||
Triode
Join Date: Dec 2021
Location: Michigan, USA
Posts: 40
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Re: The PICL V2 - a development of Karen's 2007 original
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First project.. I'd like to modify Phil's PICLV2 code for his 8K PCB to use a more recent (and less expensive) 16F18877. And with 32-K of flash memory on the '18877, compared to 8K on the '877 or '877A, a copy of Bank 2 RAM, including Phil's KB+ monitor, could be loaded from PIC flash memory into RAM at startup. Quote:
Take care. Stay safe... Last edited by Michael - K8LH; 6th Feb 2022 at 12:15 am. |
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7th Feb 2022, 3:23 am | #49 |
Triode
Join Date: Dec 2021
Location: Michigan, USA
Posts: 40
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Re: The PICL V2 - a development of Karen's 2007 original
Update... After spending a day debugging software and discovering a bad 8K RAM chip I've got my prototype board running with a 16F18887 and 8K RAM. The PIC clock is 32-MHz instead of 20-MHz (comparable to 6.4-MHz SC/MP?) and the serial port is running at 9600 baud. Phil's KB+ monitor is copied from a "page 2 image" in PIC flash memory to RAM memory at startup.
I'm pretty geeked to see it running but still lots of clean-up to do on the PIC firmware. Cheerful regards, Mike |
7th Feb 2022, 6:48 am | #50 |
Octode
Join Date: Mar 2020
Location: Kitchener, Ontario, Canada
Posts: 1,265
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Re: The PICL V2 - a development of Karen's 2007 original
Well you made that look easy
Any idea how easy it might be to move NRDS and NWDS to different output pins without changing the timing? |
7th Feb 2022, 10:51 am | #51 |
Octode
Join Date: Mar 2011
Location: North Yorkshire, UK.
Posts: 1,087
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Re: The PICL V2 - a development of Karen's 2007 original
Now that is impressive!
I've not used the 18877 before Mike, presumably Pickit 3 will do it? (I've not checked) were the PIC changes significant? (again, I'm not familiar with the 18877) Did you keep the SC/MP psuedo-instructions for serial I/O? I will be building one of yours of course! Cheers Phil |
7th Feb 2022, 11:51 am | #52 |
Triode
Join Date: Dec 2021
Location: Michigan, USA
Posts: 40
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Re: The PICL V2 - a development of Karen's 2007 original
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7th Feb 2022, 12:10 pm | #53 | |||
Triode
Join Date: Dec 2021
Location: Michigan, USA
Posts: 40
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Re: The PICL V2 - a development of Karen's 2007 original
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Quote:
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More later. Thank you all for the encouragement. Cheerful regards, Mike |
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7th Feb 2022, 1:55 pm | #54 |
Octode
Join Date: Mar 2011
Location: North Yorkshire, UK.
Posts: 1,087
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Re: The PICL V2 - a development of Karen's 2007 original
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7th Feb 2022, 2:04 pm | #55 |
Dekatron
Join Date: Aug 2011
Location: Newcastle, Tyne and Wear, UK.
Posts: 11,485
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Re: The PICL V2 - a development of Karen's 2007 original
I'm beginning to wonder if anyone prefers MBLAB X over 'Original' MPLAB. I struggle to find anyone who does.
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7th Feb 2022, 2:56 pm | #56 | |
Octode
Join Date: Apr 2018
Location: Newbury, Berkshire, UK.
Posts: 1,287
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Re: The PICL V2 - a development of Karen's 2007 original
Quote:
It's one reason I've tended to go for Arduino and now the Pi Pico - if I'm being coerced into writing with high level languages I might as well use a free open source version. |
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8th Feb 2022, 4:59 am | #57 | |
Triode
Join Date: Dec 2021
Location: Michigan, USA
Posts: 40
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Re: The PICL V2 - a development of Karen's 2007 original
Quote:
The '18877 has 32K flash memory compared to 8K on the '877 and '877A and it also has 64 banks of data/sfr registers compared to 4 banks on the '877/A. It's also less expensive ($2.43 vs $7.43 for an '877A). The '18877 also has internal weak pull-ups on the ports which are used to eliminate the external pull-up resistors on the Reset, Sense A, and Sense B switches. The code is still a work-in-progress. I have to test the Hex File Download code and I also have to figure out why I can't boot into Kitbug+ using the Sense A switch at startup. Care to take a look at the code as it is so far? I still need to add code to write whatever you've loaded into Page 2 RAM as an image in PIC flash memory. Once I get everything working for this '18877 - 8K configuration I will make a version of the firmware with the correct port/pin mapping to match Karen's schematic and your PCB. Take care. Stay safe... |
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8th Feb 2022, 1:41 pm | #58 | |
Octode
Join Date: Mar 2011
Location: North Yorkshire, UK.
Posts: 1,087
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Re: The PICL V2 - a development of Karen's 2007 original
Quote:
If you've defaulted it to Kitbug+ (2C00) thats good, then users can subsequently change the vector for other auto-run programs. All good. I'm assuming this is what you've done. So in the PIC routine startKB: Code:
startKB: ... movlw (0x2FFC-1)/256 ; KB+ entry address hi? |00 movwf P0HI ; " |00 movlw (0x2FFC-1)%256 ; KB+ entry address lo? |00 movwf P0LO ; " |00 HOME EXEC ; start KB+ Monitor ($2FFC)? |00 In KB+, the jump at 2FFC is in case the KB+ code shuffles, so no changes would be necessary to the pic sense-A-auto-start code. This really was just a very very quick scan so I've very likely missed some trick here Mike & you've got it covered Cheers Phil PS dont forget that the two halves of the 8k ram holding pages 1 & 2 are reversed... page 1 physically lives in the top half, page 2 in the lower 4k. This is only noticable when dumping the ram on a TL866 etc, in practise the PIC code straightens it out, but it could be the source of a 'Gotcha' when reworking... its like Karen inverted RAM A12 for some reason. Last edited by Phil__G; 8th Feb 2022 at 2:07 pm. |
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14th Feb 2022, 8:31 am | #59 |
Triode
Join Date: Dec 2021
Location: Michigan, USA
Posts: 40
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Re: The PICL V2 - a development of Karen's 2007 original
Thank you for the Sense A info', Phil. Sorry I missed it.
If you're interested... I reclaimed one pin on the PICL/NIBL board by implementing a 1-pin Serial interface. I used a Schottky diode and the internal pull-up on the RE0 pin on my 16F18877. An external pull-up would be required for the 16F877 or 16F877A (see below). The PIC 'TX' routine that I'm using requires a minor change and you also need to turn off "local echo" on your terminal program. This modification also fixed a problem I was experiencing. I was getting a small amount of power from my USB-to-Serial adapter through the adapters TX pin and into the RX pin (RE0) on the PIC. My power LED was partially lighted when the power switch was off but now everything is working fine. Take care. Cheerful regards Code:
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ; Serial Output. Tx char in ACC. Uses EXT, DelayCy uses TMP. ~ ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ TXX ; 9600 baud call putSer ; SC/MP & NIBL entry point |00 HOME EXEC ; |00 putSer bsf PORTE,SERLED ; activity LED 'on' |00 movlw 11 ; 1 start + 8 data + 2 stop bits |00 movwf EXT ; setup bit counter |00 clrc ; C = 0 (start bit) |00 goto TxBit ; send start bit |00 TxLoop DelayCy(104*usecs-11) ; 104 usecs minus 11 cycle loop |00 setc ; always shift in a 'stop' bit |00 rrf ACC,F ; put data bit in Carry |00 TxBit movlw b'00000001' ; assume '1' |00 skpc ; send a '1'? yes, skip, else |00 movlw b'00000000' ; prep a '0' |00 bsf STATUS,RP0 ; bank 01 |01 (needed for 877) movwf TRISE ; set 'TR' pin to a '0' or '1' |01 bcf STATUS,RP0 ; bank 00 |00 (needed for 877) decfsz EXT,F ; all 11 bits? yes, skip, else |00 goto TxLoop ; send next bit |00 bcf PORTE,SERLED ; activity LED 'off' |00 return ; |00 Last edited by Michael - K8LH; 14th Feb 2022 at 8:39 am. |
14th Feb 2022, 5:41 pm | #60 |
Triode
Join Date: Dec 2021
Location: Michigan, USA
Posts: 40
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Re: The PICL V2 - a development of Karen's 2007 original
Hey Phil (and group):
Guess what I just got going on my prototype board (see below)? I can't wait to see what you might do with all that extra memory (giggle). If I haven't said so already... Thank you for introducing me to the PICL/NIBL project and for your PCB design and software enhancements. Of course we owe big thanks and admiration to Karen Orton for sharing her experience and knowledge. I'm sorry I missed the opportunity to meet her. I knew about her projects for several years but I didn't know how to get in touch with her. Please take care. Cheerful regards, Mike |