|
Vintage Computers Any vintage computer systems, calculators, video games etc., but with an emphasis on 1980s and earlier equipment. |
|
Thread Tools |
3rd Jun 2020, 6:54 pm | #21 |
Rest in Peace
Join Date: Jul 2011
Location: Bridgnorth, Shropshire, UK.
Posts: 787
|
Re: SC/MP timing and microcode information
Hi Dom,
I've posted my latest chip-level emulator source in the Homebrew section. Enjoy |
3rd Jun 2020, 11:17 pm | #22 |
Octode
Join Date: Nov 2004
Location: Hebden Bridge, West Yorkshire, UK.
Posts: 1,885
|
Re: SC/MP timing and microcode information
Aha! Brilliant, thanks - I've just been trying to work out how they might have done the BCD add and incidentally why the ADD instruction might need an extra cycle compared to the or/and/xor instructions...there must have been a logical reason but I've not guessed it yet, or the other subtle timing differences.
I think for now I'll plough on and get it working and worry about the timings later! D |
4th Jun 2020, 11:54 am | #23 |
Rest in Peace
Join Date: Jul 2011
Location: Bridgnorth, Shropshire, UK.
Posts: 787
|
Re: SC/MP timing and microcode information
Hi Dom,
The only thing to watch out for is that jump instructions do not partake of extension register offsets. I got this wrong and my jump instructions were buggy for some while. The problem was only revealed when someone tried running a different version of SCIOS, which of course had a 90 80 (jump -128) instruction in it! When reading the SC/MP datasheet more closely, it does hint at this aspect of behaviour, so it was my bad. I have of course fixed this bug in my latest code |
4th Jun 2020, 12:13 pm | #24 |
Octode
Join Date: Apr 2018
Location: Newbury, Berkshire, UK.
Posts: 1,287
|
Re: SC/MP timing and microcode information
The other thing to watch is that calculation on the program counter and pointer registers only operate on the lower 12 bits..The upper 4 only change if you do an XPAH/XPPC instruction or equivalent, or on reset when they are zeroed.
|
4th Jun 2020, 12:31 pm | #25 |
Rest in Peace
Join Date: Jul 2011
Location: Bridgnorth, Shropshire, UK.
Posts: 787
|
Re: SC/MP timing and microcode information
Actually, my emulation DOES pass carry into the upper four bits of address calculation!
It is surprising how little impact this aspect has on the use of my emulator: most SC/MP code will be written to avoid rolling over a page boundary, so my emulator's limitation does not ordinarily get exposed. Only code which explicitly exploits the wrap-around would expose my emulator's limitation. I have never found a single instance where this is done. |
4th Jun 2020, 12:49 pm | #26 |
Octode
Join Date: Nov 2004
Location: Hebden Bridge, West Yorkshire, UK.
Posts: 1,885
|
Re: SC/MP timing and microcode information
Thanks both,
If we're talking about the 12bit pages then I had (sort of) cottoned on to that from the datasheets. Although my carry into the high byte of the pointers was a bit iffy - a negative displacement was carrying the wrong way into the top byte so $105-$87 became $27E! oops. So, what is marked on the datasheets as an incrementer needs to be inc/decrementer depending on the sign of the displacement byte? I couldn't sleep last night and was trying to work out why a binary add instruction would need an extra microcycle. The conclusions I came to were either: - it was doing an increment if there was a carry in before doing the add but then carry out would be wrong, or - it needed an extra cycle to update the status register with the Cy/Ov flags (more likely and probably what I'll do) Any thoughts? I got the perl script to generate the "ROM"/"PLA" for the microcode last night working but I've not actually started writing the microcode yet. I should think there will be a good few iterations before I get it working well enough and as I stumble across more edge cases. All good fun and thanks for the replies and encouragement! D |
4th Jun 2020, 1:32 pm | #27 | |
Octode
Join Date: Apr 2018
Location: Newbury, Berkshire, UK.
Posts: 1,287
|
Re: SC/MP timing and microcode information
Quote:
|
|
4th Jun 2020, 6:44 pm | #28 |
Octode
Join Date: Nov 2004
Location: Hebden Bridge, West Yorkshire, UK.
Posts: 1,885
|
Re: SC/MP timing and microcode information
I don't think it does it's an 8 bit ALU (shown connected to the lower busses only) and a 4 bit incrementer (which as posited above must also function as a decrementer).
I've got another poser that might be easily tested on a real CPU but not entirely clear from the datasheets would a ST ore instruction with m=1 and ptr=0 be interpreted by the CPU as STore immediate and be a NOP or would it function as a auto-indexed on P0, store at and jump to address? D |
4th Jun 2020, 11:34 pm | #29 |
Rest in Peace
Join Date: Jul 2011
Location: Bridgnorth, Shropshire, UK.
Posts: 787
|
Re: SC/MP timing and microcode information
Thought: I strongly suspect that the SC/MP has a serial ALU. That would explain why it was so perishin' slow compared to its contemporaries.
|
5th Jun 2020, 12:12 am | #30 |
Octode
Join Date: Nov 2004
Location: Hebden Bridge, West Yorkshire, UK.
Posts: 1,885
|
Re: SC/MP timing and microcode information
Possibly though I'm not sure it is quite that slow...maybe it is 4 bits?
I didn't get much further today though I have got it actually executing some instructions. My daughter had nagged me into making a NES gamepad to Amiga converter as she struggles with the bigger joysticks. At least that had lead me to digging out my PIC stuff so I mitt be able to build your emulator at some point! D |
5th Jun 2020, 12:30 am | #31 |
Octode
Join Date: Mar 2019
Location: Barry, Vale of Glamorgan, Wales, UK.
Posts: 1,363
|
Re: SC/MP timing and microcode information
Maybe it is a bit of both with the 4 bit adder applied three times...
|
5th Jun 2020, 12:33 am | #32 |
Octode
Join Date: Mar 2019
Location: Barry, Vale of Glamorgan, Wales, UK.
Posts: 1,363
|
Re: SC/MP timing and microcode information
The use of an adder as a decrementer would be lovely with the CAD/CAI (complement and add) coming through into the instruction set...
|
5th Jun 2020, 8:41 am | #33 | |
Octode
Join Date: Jan 2003
Location: Ware, Herts. UK.
Posts: 1,082
|
Re: SC/MP timing and microcode information
Quote:
John |
|
5th Jun 2020, 12:02 pm | #34 |
Octode
Join Date: Nov 2004
Location: Hebden Bridge, West Yorkshire, UK.
Posts: 1,885
|
Re: SC/MP timing and microcode information
I'll work on that assumption and try getting a 4 bit adder to work.
I've not tried the CAD instruction yet but had assumed so far that it worked rather like the 6502 where the carry flag worked "backwards" for CAD. i.e. set carry for no carry so the complement (plus the reversed carry) achieved the increment needed for a 2's complement of the operand. I have to admit I've not checked this thought out though yet. I couldn't sleep again last night but was thinking through the DAD thing and a 4 bit ALU would make sense there too...it will require an extra control signal to decide which nybble to work on but would reduce the gates needed for the ALU and would give a half carry to enable easy BCD adjustment. I'll try and get a play with it later It will require 3 cycles for an address update though which is now getting tight - before I was wondering what to do with all the extra cycles - now I'm starting to wonder the other way on! I'm starting to get tempted by the idea of making a cut-down SC/MP from TTL but I think I should probably reign in my scope-creep. I've got enough projects on the go! D |
5th Jun 2020, 12:08 pm | #35 |
Octode
Join Date: Apr 2018
Location: Newbury, Berkshire, UK.
Posts: 1,287
|
Re: SC/MP timing and microcode information
|
5th Jun 2020, 9:05 pm | #37 | |
Rest in Peace
Join Date: Jul 2011
Location: Bridgnorth, Shropshire, UK.
Posts: 787
|
Re: SC/MP timing and microcode information
Quote:
In my emulator, these PC relative accesses would reference FFFx. I get away with this because the unexpanded Mk14 only decodes the lower 12 address lines. As I say, I got away with it, but it's an aspect of behaviour that an emulator SHOULD emulate!!! |
|
5th Jun 2020, 9:26 pm | #38 |
Octode
Join Date: Apr 2018
Location: Newbury, Berkshire, UK.
Posts: 1,287
|
Re: SC/MP timing and microcode information
I should have remembered this because 18 months ago I couldn't get SBASM to assemble SCIOS from source because it thought FFx variables were out of range for the code at 0xx and despite trying I couldn't hack the SBASM code to assemble correctly under these circumstances. This means variables in, say, page 1 can't be accessed from pages 0&2 without using a pointer even if they were technically within +127/-128 bytes of the instruction.
|
5th Jun 2020, 10:36 pm | #39 |
Octode
Join Date: Nov 2004
Location: Hebden Bridge, West Yorkshire, UK.
Posts: 1,885
|
Re: SC/MP timing and microcode information
Thanks jjl, that is a very useful link and description. I will try knocking something like that up and try it out it certainly looks plausible that that might be how it is done in the sc/mp
On the wrap around thing I think i understand how it should work but will test my assumptions with some code examples. My understanding is pointer displacements should wrap with in a page and the only way out of a page is by explicitly loading a pointer with XAH but add I've only written 6 lines of sc/mp and only executed one so far I'm ready too be proved c wrong! |
22nd Jun 2020, 12:15 pm | #40 |
Octode
Join Date: Nov 2004
Location: Hebden Bridge, West Yorkshire, UK.
Posts: 1,885
|
Re: SC/MP timing and microcode information
Please could I ask any of you who has real ins8060s to take a picture of them. I'm thinking of buying one to make a testbed but the ones on eBay and ali look like they're likely to be fakes. If i have an idea of what the screen printing should look like i might be able to weed out the most likely wrong uns
D |