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Television Standards Converters, Modulators etc Standards converters, modulators anything else for providing signals to vintage televisions.

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Old 21st Apr 2004, 11:27 pm   #1
peter_scott
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Default Plug for Darius Standards Converter

I had a go at building Darius' Standards Converter and can highly recommend it.

I have made a few changes to Darius' design in an attempt to cut down on component count, namely:

Using 74HCT4046 PLL instead of Darius' discrete design. Using synchronous logic and sharing the PLL prescaling functions with the clock and synch dividers. Using a 74HCT4053 analoque switch instead of the difficult to find 7451. I had hoped to use the third switch in the pack for the CCD output switching but Darius' original discrete design gives a better crosstalk perfomance.

If anyone requires more details then I'm happy to publish them.

The converter can be seen at
http://www.scottpeter.pwp.blueyonder.co.uk/AP4.jpg

and a couple of images taken from my HMV901 can be seen at
http://www.scottpeter.pwp.blueyonder.co.uk/AP7.jpg
and
http://www.scottpeter.pwp.blueyonder.co.uk/AP10.jpg

Peter.

Last edited by Paul Stenning; 27th Dec 2004 at 1:28 pm. Reason: Fix link or code for vBulletin
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Old 22nd Apr 2004, 6:40 am   #2
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Default Re: Plug for Darius Standards Converter

Peter

Congratulations on building Darius's converter. The mods you have made sound very sensible, especially using synchronous logic. You could have used a '157 rather than a '4053 for clock switching but it hardly matters.

If you want to use a '4053 for analogue video switching then the crosstalk is indeed not very good. There are much better video analogue switches around but they are harder to find for amateur use. You can make a huge improvement by using all 3 sections of a '4053. I can't draw the diagram here but you you use the other 2 sections to switch between each input and ground ahead of the actual changeover section. This is equivalent to using 2 switches in series and grounding the wiper when off. This technique is used in all (most?) analogue switches that are designed for video.

Which phase detector are you using in the '4046? If it's the sequential one then you can reduce clock jitter by connecting a high value resistor from the PSD output to 0V. This keeps the PSD out of its tiny central dead zone. You have probably already found that the supply to the '4046 needs to be extremely well decoupled to minimise jitter.

Jeffrey
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Old 22nd Apr 2004, 10:55 am   #3
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Default Re: Plug for Darius Standards Converter

Hi Jeffrey,

Thanks for your help and encouragement.

I started with the intention of using the 4053 for the output video switching and then decided to try my luck at mopping up the clock switching in the same device. (Probably a bit too ambitious). In practice the CXLs need emitter follower buffering so I had virtually included half of Darius' discrete analogue switch anyway. Given the crosstalk problems I decided to continue using the 4053 for the clock switching and revert to Darius' video switch. The CXLs are quite sensitive to clock amplitude and offset so I had thought of using the third 4053 switch to supply dummy loads in the way you suggested
but I think Darius is getting better performance from his logic selection of CXL clocks so I may abandon my clock selection and try your approach for the video switch.

I am using the phase/frequency PSD (PC2) in the 4046. I hadn't given any thought to the crossover region but I might take a look at that. Thanks for the suggestion.

My schematic is not quite up to date but you will get an idea of it at http://www.scottpeter.pwp.blueyonder.../Schematic.jpg

This is equivalent to Darius' Blatt 4.5 and 10

Thanks again for the pointers. Any other suggestions are most welcome.

Peter.

p.s. Period picture http://www.scottpeter.pwp.blueyonder.co.uk/AP10.jpg

Last edited by Paul Stenning; 27th Dec 2004 at 1:29 pm. Reason: Fix link or code for vBulletin
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Old 22nd Apr 2004, 1:08 pm   #4
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Default Re: Plug for Darius Standards Converter

I'm always astounded when horrible bits of async logic like that divide by 566 circuit work at all reliably. The usually end up needing a small capacitor on the reset input to filter the glitches and ensure that all the flip-flops reset before the reset condition disappears because some flops reset faster than others.
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Old 22nd Apr 2004, 2:34 pm   #5
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Default Re: Plug for Darius Standards Converter

@Peter
congratulations on building the converter
and thanks for posing in the forum

@Jeffrey
Don't be astounded! Note that the frequency is much
prescaled to get high reliability. The HEF4040BPalso
don't produce glitches like TTL or HC(T) MOS. This
IC is made for this kind of divieders.

Darius
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Old 22nd Apr 2004, 3:07 pm   #6
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Default Re: Plug for Darius Standards Converter

The '4040 counters are asynchronous. This means that there is a delay between Qn and Qn+1. Over several stages this can add up to quite a large delay. It can easily be measured with a scope.

If you decode a particular count you may see glitches, depending on the actual number you have chosen to decode. This is not the worst problem. If you use this decoded number to reset the counter, each flipflop will reset at a different speed. As soon as the first flipflop resets, the decode will no longer be valid. If the delay through the decoder is less than the worst case difference in reset times of the flipflops, the design can give errors. In practice the reset time difference between flipflops is usually small, and can be shorter than the decode delay. This is especially true with the diode based decoder you have used, where stray capacitance across the resistor will slow down the rising edge of the reset pulse.

Last edited by Station X; 29th Dec 2004 at 8:06 pm. Reason: Import
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Old 22nd Apr 2004, 4:05 pm   #7
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Default Re: Plug for Darius Standards Converter

@Jeffrey
the 4040 has a common reset.
This is an advertised advantige of this IC.
I have no problems with it.
Please do not add a cap to the reset!!!

Kind regards Darius
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Old 22nd Apr 2004, 4:10 pm   #8
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Default Re: Plug for Darius Standards Converter

Hi Jeffrey,

I would like to see the counter implemented as a synchronous divide too. Although I suspect it might increase the chip count.

Peter.

Last edited by Paul Stenning; 27th Dec 2004 at 1:30 pm.
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Old 22nd Apr 2004, 4:52 pm   #9
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Default Re: Plug for Darius Standards Converter

It is physically impossible for more than 1 flipflop to reset at exactly the same instant. Even if they are on the same chip and controlled by a common reset pin. The difference may be as small as a fraction of a nanosecond but there will be a difference.
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Old 22nd Apr 2004, 5:07 pm   #10
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Default Re: Plug for Darius Standards Converter

How about we settle for a couple of HCT40103s in synchronous cascade instead.

Peter.

Last edited by Paul Stenning; 27th Dec 2004 at 1:31 pm.
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Old 22nd Apr 2004, 5:12 pm   #11
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Default Re: Plug for Darius Standards Converter

If we use 40103 we probably don't need any prescaling and I can lose a JK which brings me back to the same chip count.

Peter.

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Old 22nd Apr 2004, 6:19 pm   #12
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Default Re: Plug for Darius Standards Converter

Hi all

The HEF4040 with diode gating was used by Philips in their VR2020 VCR (1980's) on the head and capstan servo's, they switched in other diodes to give alternative divisions.

At these "sub light" speeds its not really a problem as the delays in the 4040 are so small compared to the clocking rate and the phase detector only wants to see the first edge.

I've done worse at 15MHz in a test pattern generator, but that did turn into a "glitch-a-rama" - add a 100ohm here and a 100pF there and you could tell the temperature by the ragged egdes of the pattern...

I use a PIC micro for dividers and PLL's in my Domino converter.

Well done Peter for doing it yourself.

Malcolm

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Old 22nd Apr 2004, 8:04 pm   #13
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Default Re: Plug for Darius Standards Converter

Hi Malcolm,

Thanks for the link to your converter pictures. I am very impressed. These things are clearly essential equipment for keeping old teles alive.

I must correct you on the "doing it yourself". My effort is very much Darius' design.

My design experience somewhat pre-dates PIC chips but I must learn how to use them.

Thanks,
Peter.

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Old 22nd Apr 2004, 10:34 pm   #14
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Default Re: Plug for Darius Standards Converter

Hi Peter and all

Yes I knew that it was based on Darius's design, I meant well done for actually getting down to building a working converter yourself and for tweaking his design here and there.
There was talk of publishing his design in the BVWS Bulletin, at least that would have been something 405 Line related in there.
(I will get around to writing an article for the Bulletin soon.)
I've gathered some parts together to build a version of Darius's converter myself, just for a comparison with mine.

keep up the good work

Malcolm
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Old 23rd Apr 2004, 6:32 am   #15
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Default Re: Plug for Darius Standards Converter

Hi all

Malcolm is right first I prescaled one time and it did
not count right. After two times prescaling it counted
ok. But for security I prescaled three times. At 1Mhz
the HEF4040 has no problems.

I am very impresst about Peters PLL with the 74HCT4046. I got the pdf from google. I the future
I'll use it too.
Malcolm it would be very nice to see your schematics too.

@ Peter the 7451 is on the way to scottland.

Darius
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Old 23rd Apr 2004, 7:05 am   #16
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Default Re: Plug for Darius Standards Converter

It is a common misconception that a low clock frequency will reduce glitch problems. It is easy to design systems with a very low frequency clock that suffer glitch problems. I know, I've done it at below 10kHz! 4000 series CMOS is relatively immune to glitches because the delay through gates is often longer than the glitches. Especially homebrew diode gates where the stray C across the pullup resistor increases the delay.

It is unfortunate that the designers of 74 and 4000 series logic did not make it easy to do good quality synchronous design. Very few devices have a clock enable (161,163,377) and even fewer have a synchronous reset. Most modern logic design is fully synchronous, with great care taken if you have to transfer a signal from one clock domain to another.

It is also unfortunate that excellent low cost programmable logic devices such as the Xilinx 9500 series are only available in surface mount packages. These devices make synchronous design very easy. And you can change your design without a soldering iron!

At very high speeds there is now a move back to asynchronous logic. This is due to the difficulty (and high power used) of distributing a synchronous clock in a very fast system. These async systems require special design methods. I think that some Philips microprocessors use these techniques. They are designed for battery powered equipment where power is at a premium.
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Old 25th Apr 2004, 5:13 pm   #17
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Default Re: Plug for Darius Standards Converter

I modified the interpolator.

Look at Blatt 7

I made a switch interpolator on/off.
Then I took a flip flop negativ edge triggert
and put signal a (Blatt 10 left monostable pin 13 Q)
and delayed signal b not (Blatt 5 LS14 pin4)
to trigger it. With the output I switch the interpolator.
So there are no losses in vertikal resolution, Jeffrey
told about.
Only line three and one are added and not every
following line.

Darius
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Old 25th Apr 2004, 6:45 pm   #18
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Default Re: Plug for Darius Standards Converter

Quote:
Originally Posted by ppppenguin
It is a common misconception that a low clock frequency will reduce glitch problems. It is easy to design systems with a very low frequency clock that suffer glitch problems. I know, I've done it at below 10kHz! 4000 series CMOS is relatively immune to glitches because the delay through gates is often longer than the glitches. Especially homebrew diode gates where the stray C across the pullup resistor increases the delay.
Although we are in danger of drifting off-subject here, the company I worked for when I first left school (1980) manufactured an ultrasonic inspection system for certain round engineering components. The part was rotated, and a clock was set to give 3600 pulses per revolution. Whenever the appropriate logic signals from the ultrasonics were set, various counters counted the clock pulses to give defect sizes (largest, total etc) in degrees with a resolution of 0.1 degrees. This beast used 74LS-series TTL (loads of 74LS90 decade counters and 74LS47 seven-segment LED display decoders). Although the clock was only running at a couple of hundred Hertz, there were various 0.01uF capacitors hung on reset and other logic lines to get rid of glitches and allow things to reset properly. It wasn't that consistent either - capacitors had to be added or removed during testing to get it to work reliably.
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Old 26th Apr 2004, 6:44 pm   #19
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Default Re: Plug for Darius Standards Converter

STOP!

Found a new timing for the cxl's .
Easyer logik better picture...

Darius
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Old 27th Apr 2004, 7:56 am   #20
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Default Re: Plug for Darius Standards Converter

Hi all
look at Blatt 7
the signals c, d, e must not be generated!
You save one FF and can use it for the interpolator.
Use signals f and its komplement for frequency
switching (Blatt 4).
Isn't it easy like that?
I found out that it is importand for the cxl's to
get 50% 2,9MHz and 50% 4,4Mhz.
With the old comlicated timing it is 33,x% 4,4MHz
and 66,y% 2,9MHz. This causes variationes in the
DC offset of the cxl (don't know why )

If one wants the new timing card, I'll email it.

Darius
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