Frame gated AGC modifications

[FERNSEH]

1100man wrote: I noticed in the VT9-17, there is also a connection from the AGC line to the grid of the line o/p valve. Is this some attempt to regulate changes in picture size caused by high beam current on bright scenes?

Hi Nick,
It's more likely the negative voltage from the grid of the line output valve is used for AGC delay. The APC rectifier diode V18A will not conduct until the cathode is more negative than the anode.

DFWB.

[1100 man]

Originally Posted by FERNSEH

We have to consider that a delay circuit has to be introduced so that the black level sampling takes place outside the frame sync eight broad pulses sync sequence.

Hi David,
Considering the VT9-17 circuit (post 3), which I built the other night. Looking at the anode of the gate pulse amplifier (V8B) and displaying the pulse present here with the video signal, shows that the gating pulse starts midway through the broad frame pulses and finishes after about line no 10.
Are we supposed to be sampling the frame pulses or the blank lines after them? Or a combination of both?
I really must get more books on TV circuit design theory!! It would help with these sort of projects!
Many thanks
Nick

[FERNSEH]

Extract from the text in the Spreadbury book.
ULTRA FRAME GATED A.G.C. SYSTEM.

An unusual firm of keyed AGC is that used in the Ultra V17-60, whose essential features are shown in Fig, 7.9. This system samples the black level video signal voltage during the frame sync period, instead of the back porch of the line sync period, and of course this results in very different time constants, because the frame period lasts for 14 lines instead of a few microseconds, and the AGC reservoir circuit is replenished only once every fiftieth of a second, instead of 10,00 times a second. component values are shown in Fig 7.9.
D1a acts as a sampling diode and D1b rectifies the resulting pulses.
Dia anode is DC connected to the anode of the video amplifier, so the full video signal is applied to it. It's cathode is biased by the potential divider, R4, R5 R6, R7, so that it does not conduct on the positive signal voltage. As the video signal at the video amplifier anode is negative going, peak positive excursions will occur at the bottoms of the sync pulses.
The anode of the frame blocking oscillator valve is coupled to C4 to the junction of R3 and R8 and pulses of constant amplitude are applied to C1 to the cathodes of both diodes.
On negative excursions diode D1b conducts, charging up its reservoir capacitor C9. The same negative pulse excursion also drive D1a cathode negative, "gating" the valve so that it passes current during the long framing sync pulse period. This occurs during the half-line periods at black level, the amplitudes of the resulting pulses depends of the black level voltage.
The stronger the signal, the more negative this will be, and thus the larger the pulse current through D1b.

There is another unusual feature about this receiver, in that it has four stages controlled by the AGC system.

To accompany these notes the circuit diagram appears again in the attachment.

DFWB.

[1100 man]

Many thanks for posting that. However (as is usual with me & Spreadbury!), there are a couple of things I don't understand.

The negative going video signal at the anode of the sampling diode, D1a, during the sample period, will have no video information present. It will just be the broad frame sync pulses, the tips of which are at a higher positive voltage that the black level.
During the gating pulse, D1a's cathode goes more negative so the diode can conduct. What happens then? How does this sample the black level rather than the sync tip level?

"On negative excursions diode D1b conducts, charging up its reservoir capacitor C9." So during the negative going gating pulse, current will flow from D1b's anode to it's cathode. How does that charge C9 and to what voltage?

Would it matter to the circuit function if some blank lines were sampled after the frame pulses had finished? Or does it have to be just the broad frame pulses?

Many thanks for your help
Nick

[FERNSEH]

Hi Nick,
It's the action of capacitor C1 that couples the gated negative going frame sync pulses to the APC rectifier diode D1b.
The sampling diode D1a is only conductive during the period when the gating pulse is applied to its cathode, the sync pulse represents a high positive potential to a lower value, this will after being passed through C1 be a truly negative going pulse. The frame repetition rate is 20mS and the gating pulse about 0.5mS, a ratio of 40:1. This mark to space ratio will result in the amplitude of the frame sync pulses applied to the APC rectifier having a much greater amplitude than the frame scanning time.
R3 (22K0hms) and C10 (0.02mfd) serve to delay and stretch the sampling pulse so that gating can take place outside the broad pulse train.

DFWB.

[1100 man]

Ah, I see now! The negative going sync pulses at the anode of D1a will have the sync tips at say 100V and the black level at say 80V. The capacitor, C1, removes the DC component so the sync tips are at 0V and the black level at -20V. So if the signal level changes, the sync tips will stay at 0V, but the black level voltage will alter:- that's clever!
I assume the VT9-17 works in a similar way but as the gating pulse is the other way up (due to the mutivibrator frame stage), the video signal also needs to be the other way up. Hence the triode is needed to amplify & invert the black level sampled voltage.
All very interesting. Many thanks for the explanation.
Cheers
Nick