Luminance Summing Network from TTL Circuits

[Philips210]

Hello again,

Further to my continuing development work on the Television magazine Test Card generator (May-July 1979), I'm in the process of upgrading most of the standard TTL ICs with the LS types to cut the overall power consumption. The thread on the TCG can be seen here: https://www.vintage-radio.net/forum/...d.php?t=189283

Regarding the change to LS types, I am concerned that there will be problems changing those which form part of the luminance summing network. The resistor values seem to be quite low even for standard TTL let alone LS versions. I am thinking that the resistors would need to be scaled up in value to avoid excessively loading the totem pole output stages.
Please see attached a sketch of the summing network from the original circuit diagram in May 1979 Television magazine. There were a number of errors in the original circuit diagram which I've since corrected and can be seen in the above linked thread.

One of the notable problems with this test card generator is the low level video which stems from the luminance signal. This is apparent with the original PAL encoder as well as later encoders using the TEA1002 or TEA2000 ICs. A work around in the later encoders involved a level shift/ buffer circuit which boosts the luminance signal so that the TEA encoders work correctly. This, I think, would also need applying to the original encoder so there must be an underlying problem in the way the luminance signal is built up.

In the attached pic, the luminance signal is formed by adding weighted TTL signals consisting of the Grey scale, colour bar, crosshatch, background grey, border castellations and frquency gratings signals. The result is a monochrome version of the test card. The summing network effectively produces an analogue signal from a digital one.

My question, is there a better way of going about this? I thought that the low value resistors doesn't seem right. Also, it would be good to be able to set up the level of each input to the summing network and perhaps an overall amplitude control.
If keeping the original scheme and changing to LS TTL, what would be the recommended resistor values? Perhaps it would then be in order to provide a small luminance amplifier circuit so that the encoders are fed with a suitable feed.

Any thoughts on the best approach?

Regards,
Symon

[FRANK.C]

I know little about TTL but the resistors look low.
You could scale up the resistance of resistors. Whatever load they are driving would also need to be scaled up also.
Increasing the resistance of the resistors will reduce the HF response. As the resistors and any stray capacitances forms a low pass filter.
How high you can increase the resistors without causing a problem will depend to some extent on layout etc.
I don't know of a formula that can calculate the maximum value of resistor that can be used.

As an example the Picgen 405 line pattern generator uses summing resistors as a DAC. The summing resistors in it range from 5k1 to 39k.

Frank

[TonyDuell]

I wonder if the PAL encoder circuit in the BBC micro would give any clues. From what I remember there's no specific PAL encoder chip, just TTL, resistors, etc.

[cmjones01]

The BBC micro video circuit does indeed use raw TTL to do its PAL encoding. I attach the relevant bit of the circuit diagram.

The RGB signals are generated by a ULA, which won't be TTL, but they're fed through emitter followers before being summed into a luminance signal by R137/138/139. Those resistors are quite high value (1k/2k2/3k9) but feed an emitter follower before being exposed to the outside world.

The chrominance is generated by summing the outputs of lots of LS TTL logic gates through resistors of 680R-2K2, so somewhat higher values than the Television circuit, but again they go in to an emitter follower Q9 as a buffer. The design doesn't seem to be cutting corners.

I suspect the Television circuit would struggle with LS TTL - the lower power output stages probably wouldn't deliver enough current for the existing summing circuit to work well. I'd advise either increasing all the resistor values and adding an emitter follower afterwards, or trying HC logic. I'd expect the CMOS output stages to give more consistent performance in to heavy loads than plain or LS TTL would.

Chris

[lesmw0sec]

It might be worth considering a 'virtual earth' circuit for the summing node, using a wide-band op-amp.

[G6ONEDave]

Found this site that might be of interest https://www.petervis.com/Raspberry_P..._Circuits.html

The site gives the following info for sink/source currents;
TTL=16mA
Schottky (S)=20mA
Low Power Schottky (LPS)=8mA
High Speed (HS)=20mA
Low Power (LP)=3.6mA

I've not done the maths, I'll leave that to the designer forum members, but would think that the original specified TTL chips would be suitable for the job, as long as the TTL chips are full specification and not seconds. Looking at the TTL current ratings it does suggest that LS types won't be suitable in this application, unless it can be confirmed that they won't be running at max current capacity.

Dave

[Neutrino]

According to the TI Datasheet the maximum high level output current is:
• SN7408: -0.8 mA
• SN74LS08: -0.4 mA

I think that it is hard to predict how the Luminance Summing Network will perform because it operates the TTL outside its recommended operating conditions.

The suggestion in post #4 could be worth a try. The 74HCT08 has a rated output current of ±4 mA and an absolute maximum ±25 mA. The resistor values in the Luminance Summing Network would probably need adjusting.

David

[Philips210]

Hello again.

Thank you for all your replies and suggestions, much appreciated.
The original arrangement using comparitively low value resistors was pushing things to the limit so the substitution of LS TTL would therefore be a non starter with the current resistors. The option to convert the standard TTL to HCT looks a good way to go.

I will experiment with a few resistor summing circuits and an emitter follower, perhaps after a small video amplifier.

I should have also included a copy of the original PAL encoder, this is now attached below in pic 1. It can also be seen there are very low value resistors where the luminance signal is added to the mixed syncs and the gated chroma signal.

A circuit (from Trevor, member SeeMos) to amplify the original luminance signal has been tested with good results on TEA1002 and TEA2000 PAL encoders, see pic 2. It also works with the original encoder but results are very mixed, including issues with synchronisation.


Attached are few other circuits of interest for grey scale stepped wedge generation in pics 3 and 4. These are taken from Television magazine March 1975 and January 1977 respectively.

Regards,
Symon

[Philips210]

Another circuit of interest is attached below. This is from the Colour Test Pattern Generator project in Television from May to Sept 1984 by Tony Jenkins.

Use is made of 7407 non inverting buffers with open collector outputs. Looks to be reasonably simple to adapt for further inputs and it's proven to be viable with the TEA1002 PAL encoder. It should be a similar arrangement with the later TEA2000 encoder.

The wide band op amp summing circuit as suggested by Les looks a good approach. Also, the BBC micro encoder is novel, which I'll study, thanks Chris and Tony for that and also to Dave for the sink/source current data for the various logic families.

Regards,
Symon

[Mark1960]

Try checking the output current specs for the 74ACT series.

[Chris55000]

An alternative is a two–transistor Totem–Pole NPN/PNP buffer with the emitters combined via 10 ohm resistors, with two '4148 diodes between each base, and a 10k from +5V to the top base and from the bottom base to 0V, with the signal fed to the mid–point of the two diodes!

. . .This would ensure both a symmetrical pull–up as well as a symmetrical pull–down, avoiding artefacts caused by unequal loading of the 'LSTTL outputs from the D/A Resistor Network!

Chris Williams