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Old 9th May 2020, 5:31 pm   #61
philoupat83
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Default Re: Good review of SC/MP.

oups
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Old 9th May 2020, 5:36 pm   #62
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Default Re: Good review of SC/MP.

R1 BREQ is connected to the -7v (6.8k on miniscamp 4.7k for elektor) SCRUMPI as you said 4.7k
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Old 9th May 2020, 5:38 pm   #63
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Default Re: Good review of SC/MP.

for the slep/slow test it needs an output diode in multisim is it works
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Old 9th May 2020, 8:34 pm   #64
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Default Re: Good review of SC/MP.

CE diagram I/O RAM and R/W
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Old 9th May 2020, 8:36 pm   #65
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Default Re: Good review of SC/MP.

LOAD at erratic operation see article on the scrumpi
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Old 10th May 2020, 9:57 pm   #66
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Default Re: Good review of SC/MP.

an ebauche plan of the system timing the values does not match I seek the layout of the tracks on the single-faced pcb with a single strap
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Old 10th May 2020, 10:14 pm   #67
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Default Re: Good review of SC/MP.

Looking Good! I think those two straps run from the CPU NWDS(1) and NRDS(2) to IC11 - at least that is what I have done on my Veroboard one - you can see from the photo they go to Pins 13 and 12 respectively - the rest of IC11 is a guess.

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Note that my machine does not have the IO chips and no LED on Flag1 and 2 due to lack of space. I have also not finished wiring the Address line display - that is what I am working on at the moment. From experiment I think 74C04 will be needed in the end as the C07 lights the wrong way with my setup!

To get the circuit board right will take some effort - my circuit diagram is annotated with the pin numbers I have used on my machine as a best guess with no image of the PCB.

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Old 11th May 2020, 8:45 pm   #68
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Default Re: Good review of SC/MP.

an ebauche of the pcb there remains a lot of question.
the 74c173 do not have data cabled the pcb does not show track there are holes so it should have strap
the number of resistance is 11 while the diagram shows 10
I planned two straps under the NE555
the data switches how they are connected to you action a gnd or vcc
ENIN must be at VCC but how to bring VCC
finally watch my ebauche and corrected
I would finalize with eagle mode with or without single-sided double-sided routing? should we get as close as possible to the original?
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Old 11th May 2020, 10:29 pm   #69
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Default Re: Good review of SC/MP.

Nice diagram - I will check it over carefully tomorrow - it is slightly different to the pin numbers I have used on my Vero board which I have shown on my annotated diagram so people following should be careful as the two are not exactly equal - I did what I had to do to make my wiring easier... the PCB should be as close as we can get it though! As I study your diagram I will capture the PCB pin numbers on mine as well.

the 74c173 do not have data cabled the pcb does not show track there are holes so it should have strap

I do not think this owner had these devices wired up - the articles and adverts mention you can configure them as input or output so there are holes either side and you would have to patch from the 8 data holes (like the address ones) hidden under that ribbon cable (which you show in your almost complete layout PDF earlier) to whichever side of the chip you needed.

"the number of resistance is 11 while the diagram shows 10"

Yes I have been trying to work out what R8 does - it is the one located just below SLOW and STEP - you show it wired on your diagram - I will study the circuit more carefully

"I planned two straps under the NE555"

I think you can avoid those as the TRIGGER pin 3 to the 7474 CLK can be routed under the two resistors R4 and R5 between pins to get there by looping behind pin 2 on the 7474. GND would also need to come out of the 555 looping around a pin. I do not think there are links on the original - only mention of the 20 on the top is made.

"the data switches how they are connected to you action a gnd or vcc"

The data switches on my board are wired to ground ON THE TOP terminal - this is because the mini switches connect the opposite pins - so when UP (1) the bottom two pins are connected, when DOWN (0) the data bus is grounded. This was easier for me for where my Ground BUS was (I had made some decisions before I realised). So you could just ground the Centers and then connect the Data bus to each top terminal - this will have the same effect.

I have a feeling to allow a 1 to be written to the RAM it may need a VCC or at least pullup on the other direction or the bus will be floating tri-state - I have still not worked this out yet... In which case you could not use the center pin as ground - as it would just short the power, then the center has to be the data line but, the photo does not seem to show any links to get the data lines over a ground rail on the top pins of the switches.

"ENIN must be at VCC but how to bring VCC"

ENIN could be fed from the RAM area VCC main connector as the X1 and X2 are just local loops for the 470 oscillator capacitor so it can come out there....

"I would finalize with eagle mode with or without single-sided double-sided routing? should we get as close as possible to the original? "

I said on my notes that the board should be as accurate as possible and even use white wire links for the top and not be double sided. You know that it is exactly 5 1/2" x 6" (from the Advert in ETI Dec 1976)... Hand drawn like you have will be perfect... maybe we should etch them ourselves as well...
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Old 11th May 2020, 10:45 pm   #70
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Default Re: Good review of SC/MP.

Looking at the black and white picture of the circuit board in the review article by DJD you can clearly see the Data Bus holes - it is also from here I got the fact that the 74c173 are 16 pin as it is a much clearer picture of that area on a virgin board. From here it is also obvious that the data bus goes to the top pin of the switches and you can even see a solid line running under them that I assume is ground on the center pin.

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As you can see the data bus emerges under the CPU (as well as below for the switches) and then goes up to allow patching over in two groups of four from the RAM and onto the LED buffers with wire straps bridging on the top as needed. Top RAM D0-D3 and Bottom RAM D4-D7
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Old 12th May 2020, 12:03 pm   #71
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Default Re: Good review of SC/MP.

see
https://www.reichelt.com/fr/fr/led-a...0QAvD_BwE&&r=1
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Old 12th May 2020, 12:20 pm   #72
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Default Re: Good review of SC/MP.

That's a great idea to use LEDs with built in resistance.
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Old 12th May 2020, 12:52 pm   #73
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Default Re: Good review of SC/MP.

I counted 20 strap counting only one at the level of ne555
I found 2 strap on the cpu for F0 and Sout
yes ENIN is connected to the vcc of the R8 ram and r11 asks me question it lacks tracks around r11
between the cpu and the ram there are holes
A12 corresponds to A11 towards 7400 IC11
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Old 12th May 2020, 4:39 pm   #74
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Default Re: Good review of SC/MP.

Yes my 20 straps come out as follows:

L1 GND near 555
L2 W from Pin 1 NWDS on IC1 to Pin 2 on IC11 74LS00 (Note above I incorrectly listed them as 12 and 13 which is what I have used on my prototype)
L3 R from Pin 2 NRDS on IC1 to Pin 1 on IC11 74LS00
L4 GND from Pin 8 on IC5 joining Ground Run between D4 and D3 upto IC9/10 Grounds L17-L20
L5 CE from between CPU and IC6 (BOTTOM RAM CHIP) to IC11 Pin 8
L6 A11 (marked as A12 by mistake?) to IC11 Pin 12 (also linked to Pin 4)
L7-10 D4-D7 Bus to IC6 (BOTTOM RAM CHIP)
L11 5V Strap from power feed to IC6 (TOP RAM) Pin 18 (connected via PCB to IC5 RAM)
L12-15 D0-D3 Bus to IC5 (TOP RAM CHIP)
L16 Near Pin 13 of IC11 to R/W on IC6 RAM (connected via PCB to IC5 RAM) for PROTECT and LOAD switches
L17 GND link between IC7 and IC8
L18 GND link between IC8 and IC9
L19 GND link between IC9 and IC10
L20 GND Link to right side of board near C3

I think F0 does not need a strap it can come under R9,R10 and then R2 to go up to the right of the data bus.
SOUT,F2 and F1 can all travel up to the left of the data bus - that wire you can see is more likely my L4 providing a GND between each half of the data bus - this is visible in the black and white photo.

Nice find on the ENIN wiring I agree it can route between DB7 and DB8

The holes between CPU and RAM are used in L5 and L6

I agree on A12 see my L6

I have nearly finished checking and making a few slight modifications on your diagram - still struggling with eliminating the last underlink board on the 555 though.

The photos shows an extra track running between the top of R11 and D7 from RUN/HALT so I was going to move them up by one but with ENIN now linked I do not have room!
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Old 12th May 2020, 6:38 pm   #75
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Default Re: Good review of SC/MP.

This is the sketch as far as I have made it to find routes to avoid links under the 555. I still cannot work out what R8 is meant to pull up - it must be something on the Step / Slow arrangement - I will have to have another look at your 555 diagrams. My board is built without R8 just doing what I show to make STEP just do SLOW for a short while - this usually gives a single pulse but, there must be something else like you suggested converting it a single shot monostable somehow with R8

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Note this shows that the RAM is not used with a connection of address lines as you would expect. CPU A0 is to RAM A7, A1 to A6, A2 to A5, A3 to A0, A4 to A1, A5 to A2, A6 to A3 and A7 to A4 - this will work just fine - it is a trick I have seen used elsewhere - on a Spectrum ROM cartridge to make a dump useless for a copy unless you work out it is scrambled...

All suggestions welcome on the correct SLOW/STEP and R8 circuit question.
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Old 12th May 2020, 7:42 pm   #76
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Default Re: Good review of SC/MP.

This stunt (mixing the order of address lines and the order of data lines on RAM) is remarkably common, I think it was done on the MK14 as well, there's a little warning on the circuit diagram of that machine to the effect that 'the pinning of these devices may not follow convention'. Where RAMs are concerned I think this was done mainly to make track routing easier. It makes fault finding a bit more of a headache.

When I fitted my ZX81s with 62256 SRAMs for 16K of internal memory, I dutifully routed the upper address lines to their numerically correct pins on the chip using as many wires and re-routes as necessary, but later realised that the standard way of doing it used the connections mainly in the order in which they arrived at the chip, and consequently fewer changes and flying wires.

No difference technically, it just does my head in to even think about doing it that way.
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Old 12th May 2020, 7:53 pm   #77
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Default Re: Good review of SC/MP.

That's exactly the reasoning for the ram wiring. On my MK14-board the address lines on the PROM need to be correct for obvious reasons so I changed the order of the address lines on the RAM to be the same to avoid crossing the tracks over.
On RAM of courses you can do the same to the data tracks.
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Old 12th May 2020, 10:04 pm   #78
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Default Re: Good review of SC/MP.

good evening
not the strap l5 is well SOUT to respect the order of the leds F1f2f0sout plus the rail data must be able to go on half IC9 and total IC10
the data forms a curve
for the ne555 part your reset switch is backwards the gnd position causes the reset the order is gnd 7400 vcc I managed to remove the straps on the ne555 as you had recommended
for the address very good idea I think on the ZX80 this was used led display remains true
R8 R11 poses problem pullup STEP R/H? I block on the part PROTECT SA SB LOAD
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Old 12th May 2020, 10:32 pm   #79
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Default Re: Good review of SC/MP.

Evening - thanks again for helping on this it is driving me forward!

Yes after I posted I noticed that would be an issue - I will have another look for a route as I am sure the strap you see must be for the Ground on the RAM as it is a bare wire like the other links on the board.

I do believe that the GND has to be at the top so when the switch is pushed down it causes the line to be grounded - remember these switches join the TOP pins when pushed down. This is what I had to do on my working veroboard - tested with the Oscilloscope etc. The bottom is then to +ve for when it flicks back to hold the RST high after the two NOT gates.

I think my R11 pullup is correct as I have that wired on my board and it does what I expect - it is R8 I do not yet understand so my SLOW / STEP may be incorrect.

Also as my LOAD is three position I do not actually need the PROTECT switch which is a little different so I did not yet draw that detail on how it should be on the real PCB

Did you see above that the LED drivers should be '04 type chips as I used the 07 (I have some 04 on order and they are the same pinout) but realised that as it is a low side driver the LED lights when the output is LOW as it sinks the current.
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Old 12th May 2020, 10:59 pm   #80
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Default Re: Good review of SC/MP.

In order to use mine fully I am awaiting the RAM chips. I have an SC/MP II (600) I intend to use on this board so it can be run from +5V only. I will use the I (500) when we have a real PCB and I have built a PSU. So thinking about that it would be good to add a few pads for alternate links to the PCB to allow a II (600) to be used even on the PCB.

I propose we just need one on pin20 Vss (which is GND on a II) interrupting the line to R9 - we could also bring a GND pad out just between D4 and D3 that it could be strapped to instead when using a II (600) otherwise just complete the Vss to R9 link when using a I (500).

Then you just add an extra hole joined to the +5v feed and this can be strapped to the -7 when using a II (600) which will convert Vgg to Vcc correctly and also the Pull up of BREQ by R1.

I do not think any other provision is needed to use the 600 then - this would be easier for other builders as well.
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