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Old 29th May 2020, 6:22 pm   #1
dominicbeesley
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Default SC/MP timing and microcode information

Hello scampers, I've been inspired by some of the SC/MP threads over the past year or so on here and I decided to have a go at implementing an SC/MP in Verilog (I'm just learning Verilog).

I have a number of questions but first up is the bus timings - there is some quite sparse documentation on the relationship between the clock output and the ADS signal in the datasheets but must of the timing diagrams ignore the clock - does anyone have a good source of timing diagrams showing the clock (either for SC/MP I or II).

The next one is the microcode program - I've had a really quick guess at how that might work and I've got a naive version going to just do op-code fetches but I would really like to know how it was done in the original if anyone knows.

For instance I've got a separate microcode line for each clock cycle so it is something like

1 ) increment addr/p0
2 ) assert ADS/D=A12:8,Flags=R,I
3 ) assert RD, latch D to opcode reg
4 ) check top bit of opcode and branch if 0
5 ) increment addr/p0
6 ) etc

I'm not sure how the microcode would have been done on the original i.e. would there be a microcode "line" for each of these or would they be grouped together into general i.e.

1) opcode read
2) 2nd instruction byte read?

Learning a lot, but making up more as I go along! I've no idea if anything like this would have been published but may well have ended up on a university syallabus or something at some point?

D
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Old 30th May 2020, 8:48 am   #2
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Default Re: SC/MP timing and microcode information

Excellent - interesting project. Not sure if you are aware there is a prototype VHDL MK14 from daver over on vcfed which contains an approach to SC/MP but, it does have some bugs...

http://www.vcfed.org/forum/showthrea...958#post565958

I adapted it and got it running last year on my Spartan 3 dev board but, due to some illness put it aside. I have not seen the detailed timing you ask about. The Technical Description on Page A-2 (51 of the 67 in PDF) shows the time in Microcycles for each instruction type which is pretty good...

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You can get that book and others from

https://www.curiousmarc.com/computin...microprocessor
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Old 30th May 2020, 9:00 am   #3
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Default Re: SC/MP timing and microcode information

Karen O's PIC14 MK14 emulator is cycle-exact and so must have to address some of these issues. A V1.1 version of her project including the PIC source code which powers it is attached to post #43 of this thread:

https://www.vintage-radio.net/forum/...=117728&page=3
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Old 30th May 2020, 9:11 am   #4
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Default Re: SC/MP timing and microcode information

See also this thread which I somehow missed originally:-

https://vintage-radio.net/forum/showthread.php?t=149829
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Old 30th May 2020, 10:34 am   #5
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Default Re: SC/MP timing and microcode information

Having read most of the SC/MP documentation I could find it's clear that National didn't think the timing relationship between XOUT and NAFS/NRDS//NWDS etc was important to document. For your purposes I can understand why you need to know this however. I doubt that Karen's PIC14 is going to help because while it is cycle accurate she makes no.claims to timing a accuracy down to the microsecond.
Probably the best you can do is to make measurements from a working SC/MP processor (perhaps using a variable frequency oscillator to see how the clock frequency affects timing). You probably wouldn't need more than the processor, some pull down resistors to simulate a 'NOP' instruction and perhaps a tel gate to get the instruction fetch flag as a trigger so you have a stable waveform to trigger off. And a scope or logic analyser, of course. Its possible someone here could take measurements if you sketch a timing diagram showing the timings you need.
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Old 30th May 2020, 11:11 am   #6
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Default Re: SC/MP timing and microcode information

I did find this if it's any use -
TH(ADS) = 100ns (min) 225ns (max)

p199 of this pdf
http://www.bitsavers.org/pdf/osborne...me_2_Sep78.pdf
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Old 30th May 2020, 11:32 am   #7
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Default Re: SC/MP timing and microcode information

As far as the instruction decode, the traditional way is to use a ROM indexed by opcode and cycle etc. To see an illustration of this, look at Ben Eaters series of videos where he builds an 8 bit computer on breadboards using just TTL and EPROMS. He explains how instruction decode works including ideas on how to cope with conditionals.
https://eater.net/8bit
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Old 31st May 2020, 12:33 pm   #8
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Default Re: SC/MP timing and microcode information

Thanks all so be really good pointers here. Very much appreciated!

. I'll have a proper read through all this later. The attached cycle sheet is a big help and I'll spend some time reading the links later.

I have been looking at Karen's code but the others should be a big help. So far I've got a very fat naive microcode rom but suspect I'll run out of room fairly quickly unless i can work out how to group some of the signals and decoding and conditions together!

So far I've been doing this using just the datasheets. I've never had a real scmp to test against... maybe another thing to add to my collection.

I'll carry on digging in my garage today to try and find my processor design books and I'll be back with more daft questions later.

At present once got it fetching opcodes and using the alu and a 4bit incrementer to cycle through memory but not decided how to do the actual decode step or how to handle the working out of an effective address.

I'm trying to fit this all into an EPM1270 cpld for no real reason other than I've got a fab board and a load of chips that have been begging for a use and as an exercise in learning verilog. I have some vhdl experience and I'm finding done things easier and some things more difficult (enumeration and state machines seem to require explicit design and debugging is a bit less pleasant)

D
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Old 31st May 2020, 12:42 pm   #9
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Default Re: SC/MP timing and microcode information

The smaller the better as a plug in DIP40 board becomes a reality then as an option for SC/MP replacement.
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Old 31st May 2020, 1:45 pm   #10
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Default Re: SC/MP timing and microcode information

Has anyone done a VHDL (those FPGA programmes) simulation of the SC/MP, if so it may be worth looking at the code.
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Old 31st May 2020, 2:14 pm   #11
Timbucus
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Default Re: SC/MP timing and microcode information

Quote:
Originally Posted by merlinmaxwell View Post
Has anyone done a VHDL (those FPGA programmes) simulation of the SC/MP, if so it may be worth looking at the code.
Yes post #2 has a link to an MK14 VHDL that includes an SC/MP although I have not looked at the CPU bit, only the wider machine.
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Old 1st Jun 2020, 11:24 am   #12
dominicbeesley
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Default Re: SC/MP timing and microcode information

I've been working through those TTL computer videos - they are a bit long winded but are very informative! I'm still not sure exactly how I'll do the sc/mp but it looks like my guesses weren't a million miles off!

I have given the microcode the ability to have subroutines which should help keep them manageable but not sure whether that is how it would have been done in the real thing. i.e a program counter and a link register - or would the real thing have done something more basic?

D
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Old 1st Jun 2020, 11:55 am   #13
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Default Re: SC/MP timing and microcode information

Hardware design, like software, is besr approached by getting something that works however elegantly or otherwise and then working to simplify it by looking for common elements that can be generalised. With HDL this is facilitated by using a version control system like Git,, subversion or memorial, because you can make changes, try things without worrying about being able to back out mistakes or experimental dead ends.
Get the processor working with.only a few instructions implemented then add in the rest. This way you won't have reams of repetitive code obscuring the underlying mechanism.
In short, don't be afraid to make mistakes!
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Old 1st Jun 2020, 12:09 pm   #14
Slothie
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Default Re: SC/MP timing and microcode information

If you haven't read the SC/MP Technical Description manual then that might be of great use to you. Its too big to upload here, but here's a link for the 1976 document:

https://www.dos4ever.com/SCMP/SCMP_T...tion_Jan76.pdf
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Old 1st Jun 2020, 12:42 pm   #15
dominicbeesley
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Default Re: SC/MP timing and microcode information

Thanks Slothie,

I'd not read that particular document before - thanks for the link. Though having a scan through it doesn't reveal much about the internals that isn't in the documents I already have. Where it might be useful is in the bus arbitration logic and interfacing which I've not even started to tackle yet.

I'm not afraid to make mistakes - I've been a software developer, consultant and systems analyst for 30 odd years - I spend a lot of my time fixing and then improving my mistakes!

I doubt I'll ever find the details of how it is done precisely in the SC/MP but I will try and get something functionally the same. I was hoping there might, just might, have been either some university course notes based on the actual design or a de-cap!

D
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Old 1st Jun 2020, 1:00 pm   #16
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Default Re: SC/MP timing and microcode information

Sadly the SC/MP was quickly overrun by the Z80/6502/6800 juggernaut in the late 70s and I suspect most of the university courses would consider the SC/MP too quirky to make a good subject for teaching by the time computer science degrees became a thing in the early eighties. I did a computer science degree from '81--84'and we studied minicomputer architecture as microprocessors didn't really impact it until the second half of my course by which time the poor old SC,/MP was a bit jaded. I suspect the same was true elsewhere.
The document linked does show a block diagram with data paths and does imply the use of the ALU for incrementing the program counter and address calculation (at least the lower 12 bits....) and things like that. But you are right, information is sparse. Its a shame that some of the design notes haven't leaked out from National; I suspect they were shredded years ago.
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Old 1st Jun 2020, 7:50 pm   #17
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Default Re: SC/MP timing and microcode information

I wonder if anything can be inferred from the hi-res die photo - those two big blobs - the square one and the one like one side of a pyramid look like memory so perhaps Registers on the former and microcode on the latter?

Not an expert mind.

https://en.wikipedia.org/wiki/Nation...C-MP-2_die.JPG
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Old 2nd Jun 2020, 4:46 am   #18
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Default Re: SC/MP timing and microcode information

I couldn't help noticing this very interesting thread

Some months back I developed my SC/MP emulator a bit further (or rather, a bit back) I got a 20MHz PIC16F877 running like a 4MHz SC/MP II. A full 16 bit address bus is implemented (no NADS latch!), 8 bit data bus, NRDS, NWDS plus I/O processor flags. You can build an SC/MP-like system with it BUT the buses are not true to original SC/MP timings in any way shape or form. For instance, signals like NENIN and NENOUT are not implemented at all. Oh, and it doesn't support interrupts.

I've built a new system with it but my emulation is useless for building classic SC/MP circuit boards and such (that's where Dom's solution will come in) I'll post details of my new computer in the Homebrew section when I get a minute...
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Old 2nd Jun 2020, 11:50 am   #19
dominicbeesley
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Default Re: SC/MP timing and microcode information

Thanks All,

Slothie, I was hoping that maybe it might have been used as an "archaeological" example maybe. It's not really surprising it didn't really get traction as it really as quite a quirky processor compared to the mainstream - especially with the gymnastics required to do a subroutine call!

Timbucus, I saw those on wiki - not sure that I've got the emotional strength to spend hours sifting through a picture and I suspect it would need to be a higher resolution scan for a proper decode. I know that somebody has developed some quite fancy image scanning for decoding (IIRC) the PLA in a 6502.

Karen, I'll have to dig out my PIC stuff and have a play at some point - at present that is still languishing in a box somewhere. I'm not sure how far I'll get with making this exact enough to work as a real drop-in circuit, the main problem will be getting the setup/hold timings right - either with a lot of dummy gates or with a faster internal clock and some flip-flops to delay signals. I've done this with a larger fpga in the past but it was non-trivial.

I made a bit of progress last night then decided to start again with the microcode as it was getting quite unwieldy trying to hand-code it. I've started writing a perl script to generate the verilog file for the microcode which will hopefully make it easier to change things later. For example how signals are encoded as the simplistic way I've done it so far requires 50-odd signals for each microcode line which is likely to run out of space in my cpld before I've done more than a handful of opcodes. Hopefully with the script I'll be able to make some savings and group together signals that are frequently used together.

I'm not sure I'll ever finish this any time soon it's really a learning exercise but when I've got something usable I'll post up the code and a description

D
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Old 3rd Jun 2020, 3:50 pm   #20
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Default Re: SC/MP timing and microcode information

Hi Karen,

I meant to ask - where is the latest source for your emulation? I've been using yours to check my guesses as to how instructions should work and would like to make sure I have the latest version

D
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