Non-working Commodore PET 3016

[SiriusHardware]

That shows that all address lines are good at least as far as the output side of the address buffers. If you can now do the chip-select checks that Mark suggested?

For example, put scope probe (1) on pin 20 (CS1) of UD9 and scope probe (2) on DA0, ideally of the CPU socket. If you scope the data lines there you will be looking at them after they have passed through the databus buffers. I can appreciate that you might not be able to get to the 6502 socket data pins because of the NOP gizmo sitting on top, in which case you will have to scope the data lines on the left side of UE9 / UE10.

Whatever happens on the D0 data line while the PROM pin 20 is high is not really important, but during the period when pin 20 is low you should see line DA0 go to a distinct good logic 0 or logic 1 level - if you spread the sweep time out so you can see quite a few chip select pulses on scope channel 1 you should see that during some of the chip select pulses the D0 line is driven high and during other chip select pulses the D0 line is driven low. This is because on each successive chip select, a different address in the PROM is being read from. In some of the addresses bit 0 will be a logic '0', in other addresses bit 0 will be a logic '1'.

Repeat this for PROM CS1 vs. DA1 to DA7 of the databus, again looking to see good logic levels arriving at the CPU socket during chip select=low.

Then do this for the other three PROMs UD6-UD8.

[julie_m]

Those frequencies are spot on!

The hard-wired data bus lines effectively mean the 6502 is seeing EA hex, which is a NOP instruction, in every memory location it tries to read. So the reset vector at address FFFC appears to contain EAEA, and execution after the seven-cycle reset sequence begins at that address. A NOP instruction takes 2 clock cycles; and on (or, in practice, just slightly after) the second "tock", the address lines will change to read the next instruction. So A0 will be high for two clock cycles, then low for two clock cycles, going high again after a total of four clock cycles. Another way of putting it is, one change on A0 takes two system clock cycles; and a full cycle on A0 requires two changes, or four system clock cycles. And with a 1MHz system clock, that will give a frequency of 250kHz on A0.

The ROM occupies addresses E000 to FFFF, so you should see definite activity on any of the data lines while all A13, A14 and A15 are high. Take channel one of your 'scope to one of the PROM chip select lines and channel two to each of the data lines in turn, select CH1 as the trigger source and whichever direction, rising or falling, shows anything interesting. It probably will be easier for you to do than it is for me to explain.

[ScottishColin]

OK - to make sure I'm on the right lines, I attach Pin 20 of UD6 (yellow) and Pin 33 of the 6502 socket (green).

Do they look right before I go down the road of testing everything? I can't seem to get them in a better picture by altering any of the scope options - happy to be told I'm doing it wrong.

Scope probes are both set to 10x.

https://drive.google.com/file/d/1D2Q...ew?usp=sharing

Colin.

[SiriusHardware]

You have one channel set to 1V / Div and the other set to 5V / Div - best to set both to 1V / Div so both signals are the same 'height'.

That first capture appears to show no activity (or constant logic 0 output) during UD6 chip select at DA0 on the CPU - which is surprising.