PAL videocard from Grant Searle

[nlpe1goo]

Hello,
I build a videocard from Grant Searle and have a problem with the composite video output.
I know the quality of the power-supply is important with analoge signals. But I've some noise in the video after a while of operation. (light flickering of characters, it looks like a bad contact, but this isn't so) I attached the schematic diagram. Did I forgot some special decoupling?
This card is for the SC/MP because it is controlled with the parallel port and has graphic capabilities also.

[ortek_service]

Well if the flickering only occurs after a while, then it sounds like it is due to something getting warm and not working as-well.

I assume your composite-monitor is OK with other things, and is not the problem? / you've tried it on other monitors?

So if you've got some freezer-spray etc. you could try cooling various IC's etc.

If you do have access to a 'scope, then you could maybe look at composite output and 5V power rail, at initial switch-on (when OK) and once warmed-up with problem occurring.

It seems that the ATMega328 is used to generate the composite video, and as this doesn't have a DAC, then its GPIO 'Video' output is presumably PWM'd to try and generate different voltages. Although the schematic just shows a 1k series resistor, and no ,low-pass filtering capacitor etc for this.
I assume 0V for sync, 0.3V for Black and 1.0V for peak-white have to be produced. Presumably into a high-impedance as 1K series resistor would prevent voltages above 0.5V from being produced.
So maybe it behaves differently if 75R termination is changed.

Flickering would suggest fairly-low frequency ripple etc on the signal. Whereas I would expect standard noise to be quite high-frequency and may not affect the observed video that much.
So if there is a conventional linear mains-PSU being used, then maybe a larger reservoir capacitor after rectifier and before the (on MK14 board) regulator might be worth trying.

I do recall that the large reservoir capacitor on the MK14 may only really be needed when using the VDU / may need a larger value for using with that?

Although, it could also be the main 16MHz oscillator frequency is changing slightly, and horizontal sync frequency is a bit marginal, causing some slight loss of sync? that looks a bit like flickering

[Mark1960]

The decoupling may not be effective if they are not positioned correctly between Vcc and Gnd pins. Video is generated by combination of output from two different chips so you should have a good solid ground between them and maybe take the ground reference for video out from the chip with the highest current. The decoupling cap for the atmega might need to be bigger.

[SiriusHardware]

It does look as though the video is created by combining two standard logic outputs (which can only be driven low or high) with the output levels from the two 'mixed' via resistors.

The 'video' line is driven from U2 PB0 via a 1K resistor and from U1 QH via a 470R resistor, various combinations of 'low' and 'high' on those pins will be used to generate sync tip level (both lines low), black level, and peak white.

My immediate thought is that if the composite input on the monitor has a 75R termination resistor across it internally, (as some do), then this output arrangement may not be 'strong' enough to drive such a load. I'm surprised a buffer transistor wasn't used on the 'video' output to allow for this possibility. Even Karen's 'Ortonview' conceded the need for a video buffer transistor, although she tried very hard to do everything else with nothing more than a PIC.

[ortek_service]

I hadn't spotted that U1 was also driving this - particularly as the output is unconventionally on the left-side !
But this now makes much-more sense, in being able to create various different voltage levels without a DAC (or needing 'Class D style' HF PWM).


If 5V is being applied to both the 470R and 1k resistors (effectively equating to 5V through 320R), which are then being terminated into 75R, then that would result in 0.95V into this. Which seems about right for peak white, with sync-level falling to 0V.
Otherwise, with no termination, max voltage would be 5V, which would probably be too much for non 'TTL-level' video inputs.

I believe that with SCART's Composite etc inputs, these are terminated with 75R.
But if using a monitor without built-in 75R termination, then it might be worth trying adding this externally, and seeing if this helps.
- The Black-level would also be rather too-high, so may have been above peak-white so might not have worked at all.
Or at least contrast would be much-lower than it should be.

[Mark1960]

Originally Posted by ortek_service

I hadn't spotted that U1 was also driving this - particularly as the output is unconventionally on the left-side

This style of schematic is always hard to follow, putting a bus around and between components with all components connected to a common bus, including power, decoupling etc is in my view worse than a netlist circuit diagram without the bus.

[nlpe1goo]

Thanks for the responses.....
I draw all of my schematics with CPU things using a bus. I find this better to read, but could be a little difficult to read for others. But for the PCB it doesn't matter .
In other video card schematics I found a buffer transistor as one of you mentioned also.
The PB0 of the atmega is the composite sync line and the QH of he shiftregister is the video output. I'll put a buffer transistor in the schematic and post this here later. Today I've some other things to do first.
One thing I didn't tell yet is that when I used a powersupply which couldn't handle the peak currents the video buffer in the atmega got corrupted and I got random blocks and lines on the screen. Using a better supply solved this. Will be continued....

[nlpe1goo]

Here the newest schematics with the buffer for video.. I've do some test first on it later. C6 and C7 are the same as C2 and C3, placed there to get also a smd version as option.

[ortek_service]

Having Vcc & Gnd on a computer 'Bus' is also rather unconventional (Even if using a multi-signal 'Harness' on some CAD systems)
- As normally power (and certainly Gnd) are Global across all sheets / at least all common on a sheet.


Unfortunately, adding a buffer transistor as on this updated schematic actually makes matters worse!
As the 470R (R1) & 1k (R2) are no-longer terminated in 75R, so there won't be the correct voltage output-levels.
And R5 (1k) bias to +5V Pull-up, further turns-on the transistor, making output even higher.
- So transistor output will be often around +5V (-Vbe) / when sync and video are low, it will still be > 1V.
Therefore, R5 should really go to ground, and be 75R - As without the buffer transistor inserted, and terminated as intended.

However, as there's now a buffer, it would probably be better to make these resistors all much-higher, to make best-use of the buffer and save wasted power - So maybe multiply by at least 10, using 4k7, 10K, and 750R to ground on the base-side of the transistor.

Although, as a BJT silicon transistor emitter-follower Buffer introduces a 0.65V voltage drop, then some adjustment of the values on the base-side is necessary, to ensure the correct output levels - Which still varies depending upon termination loading, with a 47R (R6) series resistor.
Making this series output resistor much-lower would help in making output voltage less load-termination dependent
- But less-protection for the transistor against shorting-out the output.
And having some series-resistance on the output, increases output impedance to 75R to be a better match to the cable / termination.

[nlpe1goo]

Originally Posted by ortek_service

Having Vcc & Gnd on a computer 'Bus' is also rather unconventional (Even if using a multi-signal 'Harness' on some CAD systems)
- As normally power (and certainly Gnd) are Global across all sheets / at least all common on a sheet.

I've never learned drawing via CAD systems. Thanks for your advice.

Originally Posted by ortek_service

Unfortunately, adding a buffer transistor as on this updated schematic actually makes matters worse!
As the 470R (R1) & 1k (R2) are no-longer terminated in 75R, so there won't be the correct voltage output-levels.
And R5 (1k) bias to +5V Pull-up, further turns-on the transistor, making output even higher.
- So transistor output will be often around +5V (-Vbe) / when sync and video are low, it will still be > 1V.
Therefore, R5 should really go to ground, and be 75R - As without the buffer transistor inserted, and terminated as intended.

However, as there's now a buffer, it would probably be better to make these resistors all much-higher, to make best-use of the buffer and save wasted power - So maybe multiply by at least 10, using 4k7, 10K, and 750R to ground on the base-side of the transistor.

Although, as a BJT silicon transistor emitter-follower Buffer introduces a 0.65V voltage drop, then some adjustment of the values on the base-side is necessary, to ensure the correct output levels - Which still varies depending upon termination loading, with a 47R (R6) series resistor.
Making this series output resistor much-lower would help in making output voltage less load-termination dependent
- But less-protection for the transistor against shorting-out the output.
And having some series-resistance on the output, increases output impedance to 75R to be a better match to the cable / termination.

So adding the buffer as I did is not so smart anyway I could leave it as it was originally. Adding a 1uF capacitor across the power lines of the ATMEGA could do some better filtering of the powerlines.

[ortek_service]

Originally Posted by nlpe1goo

>>
>>
So adding the buffer as I did is not so smart anyway I could leave it as it was originally. Adding a 1uF capacitor across the power lines of the ATMEGA could do some better filtering of the powerlines.

Well a buffer can make the output voltage levels rather-less sensitive to exact termination resistance so isn't necessarily a bad idea. But it does make thinks a bit more-complicated, in that you need to recalculate all the resistor values that feed it, to give the correct voltage levels at the output.

And ideally a 'scope (even a cheap low speed hand-held / PC-based one), to check it is all working as expected.
- Which would still be useful, if you are not sure that your current composite input monitor is terminating in 75R, and voltage levels from original circuit are correct.
It is in-theory also possible to check these with just a DMM on Volts etc, if you can 'Single-Step' the video-circuit through the various combinations of Video & Sync logic states (Could remove IC's and tie these Low / High, although the IC's outputs may not quite go as Low / High under load).


Although no harm in trying adding extra decoupling to see if that helps.

[Maarten]

Originally Posted by Mark1960

This style of schematic is always hard to follow, putting a bus around and between components with all components connected to a common bus, including power, decoupling etc is in my view worse than a netlist circuit diagram without the bus.

Philips knew how to do this in a mostly non-confusing way back in the 1970's (at least in continental TV schematis). You could mostly see the important circuits, structures and connections immediately and then follow the bus to find how parts of the schematic interacted. They never included power lines, choosing to use triangular markers for those. Bang & Olufsen took one look at the Philips method and adapted it perfectly to fit their utterly confusing schematic style... A hybrid between bus and direct style schematics may be the best solution with today's digital circuits as long as the Philips style is followed, not the B&O style.

[TonyDuell]

Originally Posted by Maarten

Philips knew how to do this in a mostly non-confusing way back in the 1970's (at least in continental TV schematis). You could mostly see the important circuits, structures and connections immediately and then follow the bus to find how parts of the schematic interacted. They never included power lines, choosing to use triangular markers for those. Bang & Olufsen took one look at the Philips method and adapted it perfectly to fit their utterly confusing schematic style... A hybrid between bus and direct style schematics may be the best solution with today's digital circuits as long as the Philips style is followed, not the B&O style.

I think it depends on what you are used to. I am currently working on a Philips P2000C computer and have the official service manual with such circuit diagrams for the 2 main boards. I do find having somewhat unrelated signals grouped as bus to be confusing.

Maybe because I learnt a lot from them, I find DEC circuit diagrams of things like PDP11s to be very easy to follow. And they rarely 'bus' any signals at all

I am happy with related signals being shown as a bus -- in the example here I'd take the 8 input bits from the host as a bus, the data inputs to the shift register as another bus, but I'd not include any other signals with them. Or put said other signals in a bus.

[Realtime]

Hi Nick, here are simulations of the videodisplay2 circuit without a buffer and videodisplay3 with buffer. The simulations show 2 pixels generated on a video line between 2 hync pulses.

The simple resistor network works well. It assumes the monitor is terminated in 75R. The video ouput from the HCT shift register needs to drive 0.7V into 75R = 9mA. This is well within the capability of HCT logic. The ATmega needs to drive 0.3V into 75R = 4mA. Again no problem. The drawback of this circuit is that the output impedance is much higher than 75R so you will get reflections that could degrade the video quality.


v3 with the buffer is not good! The output has the correct video to sync ratio, but voltages are way too high.


This is the circuit from the Realview video adapter, modified for HCT and ATMEGA output voltages (4.8v and 4.1v respectively - from the datasheets). This produces the correct video and sync levels and terminates the video output at each end of the cable (R3 is part of the driver, R4 is in the video monitor). This double termination means the transistor is driving 26mA for peak white video, so decoupling capacitors at the transistor collector are needed. 1% resistors are recommended as the circuit is quite sensitive to tolerancing, particularly R2.



Hi-res images are attached in the zip file. Hope that helps

[nlpe1goo]

Thanks,
I've another problem: I measured the output and detected 25mV noise on the signal. This results in flickering characters I think. The frame sync is 50.0126Hz, so that is alright. The line sync didn't lock....I've only 5V switching power-supply available. I don't trust them. I'll try a linear one later on. Thanks for calculating the right values of the resistors used in the buffer, but in the original setting it should work also as told.

[ortek_service]

Hi Nick,

I wouldn't expect 25mV of noise on this signal to cause that much of an issue - And if high-frequency, then maybe not the cause of the flickering.

It's odd that you say that Line-sync didn't lock - I presume just on your 'scope (I assume you've used one to measure the field-sync freq. and the 25mV of noise)?
As presumably your monitor must be locking to line-sync OK, otherwise you wouldn't be able to get a stationary picture on the screen, just a lot of random stuff on the lines.

So might need to play around with the 'scopes trigger mode / polarity / level settings / timebase (and so sampling rate, if using a non-analogue DSO), to get it to reliably lock to the line-sync pulses.
(Some old Analogue 'scopes often used to have specific trigger-modes for video line / frame rates)

Maybe you could attach a picture of 'scope display, to compare with Realtime's simulation pictures / show the 25mV noise?


If you do a 7805 etc. Linear Regulator IC, then you could try powering the video-circuitry / the MK14 as well, from this (as it was originally designed to be powered from). But would need to find a PSU to provide around 8Vdc into that (+12V may be OK, with enough heat-sinking on the the 7805).


Yes, the buffer circuit configuration Realtime attached / had simulated (in LTspice?) is what I'd envisaged, with pull-up changed to pull-down on input side, and rather different values.
Although I would've tried a bit-higher-values on the input-side, that avoid loading the HCT & ATMega outputs too-much so that the high-level voltages from these are a bit-closer to the supply-rail to avoid complications of having to account for that / concern that the output drop / resistance may vary between different samples of the devices / different makes of HCT.

[nlpe1goo]

Originally Posted by ortek_service

Hi Nick,

I wouldn't expect 25mV of noise on this signal to cause that much of an issue - And if high-frequency, then maybe not the cause of the flickering.

Sorry but I made a mistake: the noise was a quarter of a 1V/division square. So it is 250mV. The screen looks very stable but noisy.
I paused my research because I have to wait for a 5 Volt linear supply to try. I've a lot of other work to do... because my cellar will be repaired in my home. (Two years ago I had a flooded cellar wich caused a lot of damage.)
Another thing is that I don't have a MK14 but a replica of the Elektor NIBL basic computer that I had redesigned with a 8255 I/O port on it.

[ortek_service]

250mVp-p is rather a lot of noise - About a third of the 0.7Vp-p black-level to peak-white video-amplitude!
So if wideband and not just high-frequency, then could well be causing some noticeable effects on the display.

And is a lot of noise, even for a 5V switched-mode PSU! With risk of affecting noise-margin of TTL logic if present on Logic-Low and Logic-High levels.