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Television Standards Converters, Modulators etc Standards converters, modulators anything else for providing signals to vintage televisions. |
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27th Jul 2015, 12:42 am | #1 |
Heptode
Join Date: Jun 2006
Location: Ware, Hertfordshire, UK.
Posts: 988
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Standards Converter Experiments
Hi All,
I'm currently doing some standards converter experiments. I might later on design one using more recent components, but for now I'm using 1990's components (easily purchased on the internet) as they are all though hole. The Write clock is 9.75MHz derived from a PLL which is divided by 624 via PIC to produce 15.625KHz to compare with the incoming line syncs. The Read clock is from a 6.4MHz crystal. The conversion is done using two FIFOs (one for interpolation). These are manufactured by IDT and work very reliably. I originally tried Cyprus FIFOs, but I found that after a few minutes use the internal memory use register would become corrupted. Storage control is by simply checking the state of the Half-Full flag at each line sync and enabling/disabling the Write clock to match it. It works quite well without interpolation (both FIFOs being fed with the same lines), but the interpolator when switched in displays a significant phase error which also drifts. I need to spend some more time debugging, as most of the problems seem to be due to crosstalk between the Write and Read clocks. Will post again after more experiments... Andy
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28th Jul 2015, 7:16 am | #2 |
Heptode
Join Date: Jun 2006
Location: Eindhoven, Netherlands.
Posts: 640
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Re: Standards Converter Experiments
That is a very encouraging result Andy!
Not a lot of people have the knowledge (and courage!) starting designing a standards converter. Please keep us informed about progression. Jac |
29th Jul 2015, 1:55 am | #3 |
Heptode
Join Date: Jul 2009
Location: Stoke-on-Trent, Staffordshire, UK.
Posts: 719
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Re: Standards Converter Experiments
Interesting project Andy.
I made a couple of simple standards converters along similar lines a few years ago... the FIFO's were harvested from Videocrypt decoders as used in most old analogue satellite receivers and the rest was mainly HCT logic for the same reasons as yours... through hole prototyping. I never did get round to doing the interpolation: the intention was to use a fast eprom as a LUT provided with with line and previous line to give an interpolated one, as suggested by Jeffrey Borinsky. As per Domino? I even got as far as programming the eprom before I ran out of enthusiasm. I wonder if I can find any of my notes. Very interested to see how you get on. Pete |
30th Jul 2015, 12:26 am | #4 |
Heptode
Join Date: Jun 2006
Location: Ware, Hertfordshire, UK.
Posts: 988
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Re: Standards Converter Experiments
Thanks to Jac and Pete for the encouragement.
Yes the Domino uses an eprom for the interpolation. Doing it the analogue way is ok though, especially if you use something like the ADV7125 which is three DACs for the price of one (though here I'm using 2 x TDA8702). I've had a look at the Write clock timing. The first picture shows the Write enable pulse and the Write clock (actually the Write enable pulse is actually upside down in this picture as I've captured the interpolator Write enable pulse by mistake, but it still shows the timing). You can see the the Write pulse transistion cuts a clock pulse which led to a small amount of jitter. I've now inverted the VCO clock feed to the PIC and so in the second picture you can see that the Write enable pulse changes in step with the clock pulses. The third picture shows the Write enable waveforms (the right way up this time) for the main store (the lower trace) and the interpolation store (the upper trace). You can clearly see that most of the time 1 in 3 lines are dropped, but occasionally 1 in 2 lines are dropped (we need to lose 1 in 2.83 lines to get from 625 to 405). The main store Waveform is shifted during each line sync pulse, it shifts to become the interpolation store pulse. I'm still having problems with the interpolator output being all over the place. It turns out that something is not quite right with the boot up reset procedure for the FIFOs because the interpolation FIFO is becoming over full, hence the timing errors. I will have to investigate further. Regards Andy
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31st Jul 2015, 10:06 pm | #5 |
Dekatron
Join Date: Mar 2005
Location: Gateshead, Tyne and Wear, UK.
Posts: 7,444
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Re: Standards Converter Experiments
Hi Andy,
Encouraging results. I did try using FIFOs way back in 1992, again the results were quite good. The write clock frequency was 10.125Mhz (648 X 15,625Hz). Read clock frequency was 6.561Mhz. (648 X 10,125Hz). DFWB. |
31st Aug 2015, 9:07 pm | #6 |
Retired Dormant Member
Join Date: May 2009
Location: Fresnes, France
Posts: 124
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Re: Standards Converter Experiments
Hi Dear Andy,
Nice Job. Concerning the TDA8702, you can put all the time the chip ON. In my design, I have some problem because when enabling the TDA8702, some strange dots appears. I will suggest more PSU for each function. My first converter is a 625 to 819 B&W for French Standard. I put only one 7805 for TDA8708, TDA8702 and the synch separator=> a lot of noise and some error during operation of the TDA8708A:sometime, i was loosing bit 0, 1 & 2. I put a 7805 for each IC and a strong filter => no anymore problem. You can find my converter with all the code and wiring diagram in this section. If you need more IDT FIFO, I have a very big stock=> you just need to pay shippment. I don't understand why you are using 2 * TDA8702: can you supply the wiring diagram? Thank you very for all informations. Fred.(Pitbuell94). |