26th Oct 2020, 3:02 pm | #621 |
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Re: Mk14 vdu
In this case the quarter cycle clocks are 62.5nsec but you're right Phil G.
I've made a minor change which might stop juddering in A version. If not, ignore and destroy all evidence of attachment. The secretary will disavow any knowledge of your actions. |
26th Oct 2020, 3:09 pm | #622 | |
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Re: Mk14 vdu
Quote:
1/20,000,000hz = 50ns per clock cycle Karen. 200ns per '4 clock pulse' instruction cycle. Only 50ns for a previous write to settle before it is read by the next instruction - doesnt take much capacitance to hold the pin voltage down for 50ns Sorry to push it! could this '250ns' whoopsie affect video timing calculations? Last edited by Phil__G; 26th Oct 2020 at 3:16 pm. |
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26th Oct 2020, 3:12 pm | #623 |
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Re: Mk14 vdu
Fun Fact: The VDU project runs on 16MHz, not 20MHz?
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26th Oct 2020, 3:28 pm | #624 |
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Re: Mk14 vdu
Ow cripes I'm really sorry everyone. I'm going to keep out of this now, honestly trying to help but making stupid assumptions
Is there a way to delete them once the edit window has passed? Sorry all. (scurries away, tail between legs...) AND somehow (?) I entered a duplicate post on the previous page... Last edited by Phil__G; 26th Oct 2020 at 3:44 pm. |
26th Oct 2020, 3:33 pm | #625 |
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Re: Mk14 vdu
It might be possible to test the theory of a shortened write cycle by adding an AND gate on the NENIN of the SC/MP. Inputs to the AND from NWDS and NENIN from the PIC.
This would allow a write cycle to complete before the SC/MP is kicked off the bus, but would depend on a delay between setting NENIN high from the PIC and the PIC starting to access RAM, that would need to be greater than the Pulse width on NWDS. 500 ns at 4MHz. Last edited by Mark1960; 26th Oct 2020 at 3:36 pm. Reason: Add NENIN from PIC as input to AND gate. |
26th Oct 2020, 3:38 pm | #626 |
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Re: Mk14 vdu
Unfortunately not, they are there FOREVER as I have also found to my considerable regret from time to time.
You just have to remember we are dealing with the High Priestess of PIC here - I'm mostly too scared to make suggestions, because I know I'll be wrong. |
26th Oct 2020, 3:38 pm | #627 |
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Re: Mk14 vdu
Come on back, Phil G.
The point you were making would be valid whether the VDU was clocked from 16MHz OR 20MHz. I don't think anyone here means to rebuke so let's all stay friendly. |
26th Oct 2020, 4:30 pm | #628 |
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Re: Mk14 vdu
Just ordered a couple of 877 (non A) from RS so I can parallel Tim's beta testing with both types. Thanks to Phil__G for finding the link to the RS part number so I didn't have to.
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26th Oct 2020, 5:01 pm | #629 |
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Re: Mk14 vdu
Excellent - do you think you will be able to test the 10K NWDS pull-up as well to see if the corruption appears / gets worse for you?
It’s occasional nature and relationship to NWDS getting back high gives credence to the time to complete theory and would also account perhaps for it appearing in both banks on charset as that must be a parallel write to partially changing address and data bus. |
26th Oct 2020, 5:44 pm | #630 |
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Re: Mk14 vdu
I can give that a go if you like but you might remember that when I fired up the very first firmware it didn't work because I had (...Durr) forgotten to include a pullup at all on NWDS. From that we can already say that there is a threshold resistance above which things will start to go wrong. Since I actually put a pullup on NWDS it has always been 4K7, SOC's recommended value.
Since you then put a definite 4K7 on yours, yours has also been OK in respect of the 'charset stray character' problem so we could conclude that as long as the NWDS pullup is the value it is supposed to be, it works. But if you're just curious to know whether a non-canon 10K pullup causes similar effects for me then I'll try that. |
26th Oct 2020, 6:09 pm | #631 | |
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Re: Mk14 vdu
Quote:
Edit: The more writes a program does the greater the risk that NWDS is still low or climbing when the PIC transitions the address bus most likely but, from the corrupt bit 7 even the data bus. Edit: For those not familiar MINEFIELD is a character mode program that crashes - it does a lot of writes... Last edited by Timbucus; 26th Oct 2020 at 6:15 pm. |
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26th Oct 2020, 8:46 pm | #632 | ||
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Re: Mk14 vdu
First of all, regarding Karen's firmware modified with a view to both graphics and characters running at the same baudrate (FW posted in #612)... unfortunately this will not assemble for me. After the usual many warnings there are a large number of errors which break down into two types, examples of each below:-
The first looks to me as though the assembly process has overrun the available code memory. The second looks like a missing label definition. Quote:
Quote:
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26th Oct 2020, 8:49 pm | #633 |
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Re: Mk14 vdu
The firmware from #621 does assemble for me so I'll now try that to see if it has fixed the 'A suffix shudder'.
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26th Oct 2020, 9:11 pm | #634 | |||
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Re: Mk14 vdu
Quote:
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26th Oct 2020, 9:12 pm | #635 |
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Re: Mk14 vdu
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26th Oct 2020, 9:17 pm | #636 |
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Re: Mk14 vdu
And sorry to say that with firmware from #621, graphics mode only and 'A' suffix PIC, the shudder is still there. Thanks for trying anyway, Karen. The only thing I can point to as a clue is to say again that this problem (graphics screen shudder, 'A' suffix PIC only), first appeared in the first optimised version.
In the two released versions prior to that, graphics mode rendering was rock steady even with an 'A' suffix PIC, so something in the modifications which were made after those 'broke' graphics mode for 'A' suffix devices from that point on. Last edited by SiriusHardware; 26th Oct 2020 at 9:25 pm. |
26th Oct 2020, 9:28 pm | #637 | |
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Re: Mk14 vdu
Quote:
Then if we can cure the occasional memory write errors it will be perfect. Karen - if there is an easy way to cause a fixed delay when the PIC asserts NENIN then we should be OK as the 352 original FW did not have any memory corruption events as my youtube video showed - the (theorized) memory write problem only began with the optimized firmware which as I understand it gave more time with NENIN low for the CPU to work. |
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26th Oct 2020, 9:47 pm | #638 |
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Re: Mk14 vdu
If anyone is interested the changes that caused the graphics judder on A parts and started the memory write errors occurred between #352 and the optimized version. This is the difference between #352 and the latest #621 (assuming we consider the #612 version a development branch).
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26th Oct 2020, 10:03 pm | #639 |
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Re: Mk14 vdu
I've just had 'Minefield' running on both OrtonView and SOC VDU - infuriating game, especially when you miss one of the very last mines and get sent all the way back to the beginning again.
On OrVw I don't have to play it for long before strange things start happening, random bits of tank all over the screen or similar. I can only assume this is due to the game code getting gradually corrupted. On SOC VDU the game kept running for as long as I had patience to keep playing it for - in both cases with the usual NWDS pullup value of 4K7, I didn't need to bend that value in order to see Minefield failing quite soon when running on OrVw. Luckily, every time the code got smashed up it was a simple matter just to reload it. |
26th Oct 2020, 10:18 pm | #640 | |
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Re: Mk14 vdu
Quote:
Edit - the F fire trick is useful when you get reset as it will pulse the tank forward a little faster so you get to the previous place with your new tank quicker. |
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