Re: 819 line standards convertor.
Hi Frederic,
"When I design my VHDL code, I suppose I build the design of the read part and write part as 2 single separate design part?"
This should be one design but two separate processes. You can break the processes out into modules, but there really is no benefit on a design this small.
"Only a signal coming from the write part give the information to the read part that there is some data ready to read."
As long as you synchronize this to the read clock with at least two FF's, this will be fine.
"Because I start to read 819 signal after 2 lines coming from 625 and because the video signal comes at line 23, I start to read line for 819 signal at the start of line 25.( I need a minimum of 2 lines to start my process...)."
Yes, you need to offset the field on the 819 side from the 625 side by the time it takes you to process an output line, which would be two 625 lines plus any overhead.
"So, the start of field one in 819 starts at the beginning of line 621 of 625 lines standart."
This sounds about correct, but will be dependent on your processing overhead, so may need to be adjusted.
Darryl
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