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Kat Manton · 2nd Jun 2006, 2:44 am

Hi,

...and then for the "Mk3" I'll proably take Jim's analogue video section and add a better SPG (I do digital design much better than analogue, really!) On the Pye monitor I do see slight problems with the interlace, lines are pairing slightly rather than being evenly spaced - it was expected that soon enough I'd find something which didn't like the taste of XORed H/V sync; I'm actually pleased that the Pye monitor's fussy as I can test out better SPG circuits with it

Oh, in between doing bits of website I'm investigating the pixel clock rates on various cards. (I can't concentrate on one thing for extended periods of time, it's better I have several projects running in parallel and switch between them as the mood takes me.) So, I'm looking at how the pixel clock is calculated, what reference crystal is used on various cards, and what range of values the PLL configuration registers can take. It all seems pretty straightforward.

I can work this out from study of the C source code for the drivers (I love Open Source.) I should be able to work out exactly what specific pixel clock rates can be obtained from various cards (without having to own the card), probably by setting up a spreadsheet or hacking a quick bit of C together (probably by copying chunks of code from the driver) to do the calculations. Once we know exactly what pixel clock rates specific cards can do, we can identify which cards should work or not, and select pixel clock rates to give the best timings.

It also seems that in at least one case, the "12MHz limit" is arbitrarily hard-coded and a patch to the driver may well mean more cards can go lower than 12MHz than originally suspected.

Regards, Kat

2nd Jun 2006, 2:44 am	#83
Kat Manton Retired Dormant Member Join Date: Jul 2005 Location: West Yorkshire, UK. Posts: 1,700	Re: PC as a standard convertor Hi, ...and then for the "Mk3" I'll proably take Jim's analogue video section and add a better SPG (I do digital design much better than analogue, really!) On the Pye monitor I do see slight problems with the interlace, lines are pairing slightly rather than being evenly spaced - it was expected that soon enough I'd find something which didn't like the taste of XORed H/V sync; I'm actually pleased that the Pye monitor's fussy as I can test out better SPG circuits with it Oh, in between doing bits of website I'm investigating the pixel clock rates on various cards. (I can't concentrate on one thing for extended periods of time, it's better I have several projects running in parallel and switch between them as the mood takes me.) So, I'm looking at how the pixel clock is calculated, what reference crystal is used on various cards, and what range of values the PLL configuration registers can take. It all seems pretty straightforward. I can work this out from study of the C source code for the drivers (I love Open Source.) I should be able to work out exactly what specific pixel clock rates can be obtained from various cards (without having to own the card), probably by setting up a spreadsheet or hacking a quick bit of C together (probably by copying chunks of code from the driver) to do the calculations. Once we know exactly what pixel clock rates specific cards can do, we can identify which cards should work or not, and select pixel clock rates to give the best timings. It also seems that in at least one case, the "12MHz limit" is arbitrarily hard-coded and a patch to the driver may well mean more cards can go lower than 12MHz than originally suspected. Regards, Kat Last edited by Kat Manton; 2nd Jun 2006 at 2:59 am.