I managed to save a logic trace of a good boot and a bad boot (unfortunatly the R/W pin was not recording on the good boot
It shows something quite interesting!!
John just to answer your points first.
NMI is connected to PA which also triggers the RESET. NMI goes HIGH significantly before the RESET goes HIGH, and stays HIGH until the power is turned OFF
The circuit uses address bits A11 to A15 (0x1000 to 0x17FF) to externally turn the RESET line OFF via logic chips SN1 and SN6, resetting SN3.
However my problem seems to be with the first boot instructions, as I have compared the first instructions after RESET goes HIGH, and there is an immediate difference I can not explain.
On the good boot the Address sequence was:-
FFFE, FFFF, C3CD, C3CE, C3CF, C3D0, C3D1
The first two being the reset addresses and read FF, and CD on the DATA lines from ROM1 respectively.
These are all ROM2 Addresses
On a bad boot the sequence was:-
FFFE, FFFF, FFCD, FFCE, FFCF, FFFF, FFFF
these all being ROM1 addresses! (A13 to A15 are chip select bits)
The RESET addresses also reads FF and CD from ROM1 respectively.
Any idea why the RESET addresses both read the same results, but immediately the 6802 starts outputting different addresses?
It looks like the most significant byte is getting corrupted to 0xFF
I replaced SN9 and SN11 in case they were loading the address outputs.
All other 6802 pins are identical (but I will confirm tomorrow as not monitoring at moment, but have checked they are all correct to schematic)
I have just noticed that the addresses A8 to A15 are 0xFF (and occasionaly they change to 0x00) for a long time, before it starts addressing other ROMs
These result in reading in 0xFF on the data lines (confirmed by looking at the ROM image)
Could the 6802 be faulty?
Peter