[pitbuell94]

Hi everybody,

I'm back concerning this topic.

I spent a several nights and I made several nightmare too to solve the problem of the software.

The system is not running at this moment but it is still in progress...

The problem come from the design of my FIFO...

I haven't seen my FIFO design did not contain enough slots.

Now, my fifo run in demo mode by using ISIM from XILINX.

The next step is to build the hard part on veroboard.

In attached files, there is the good running design of the fifo and the testbench to check it.

As we said in France " Patience et longueur de temps font plus que force ni rage" => "Patience and time do more than force or rage ..."

Have a nice day.

Frédéric Cabanes.