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Old 20th Mar 2019, 4:18 pm   #139
FRANK.C
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Join Date: Feb 2006
Location: Roscommon, Ireland
Posts: 732
Default Re: Hedghog standards converter

Hi Nick
Well done for getting that sorted.
The TVP5150 must be pretty robust to withstand two video data pins being tied together.

The fact that you have activity on the least significant bit to the DAC on the test card and none when video in is selected is strange.
The output from the FPGA is obviously OK as it is working when test card is selected. All the video data pins from the video decoder must be connected OK to the FPGA as if even one was missing the FPGA would not be able to extract the syncs. As you found if two video data pins are shorted together (depending on which two) it can still be possible for the syncs to be extracted.
Considering all that, it looks as if the problem is internal in the FPGA,

To answer your question of why 9 bits and not 8.
Within the converter the video expands to much more than 8 bits in places. For example the output from the interpolater is 18 bits wide. The output of the interpolater is the result of adding fractions of 6 input lines together so there will be fractions in the result. After some processing the 18 bits gets truncated to 8 bits so it is able to fit into the time redistribution memory. After all the processing the video is 8 bits wide.

But this is just video no syncs. The sync value is added to the video before been sent to the DAC. The video takes up almost all of the available room in the 8 bits so an additional bit is needed to accommodate the syncs.

An explanation of the R2R DAC can be found here. It is explained there a lot better than I could explain it.

Frank
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