[Mark1960]

It seems I was chasing two issues. A tight loop with ILD at B10 was changing both F10 and B30. Adding an RC delay fixed the spurious writes to F10 but not B30, that turned out to be a faulty RAM chip, also found another faulty ram chip while swapping out to get it working. So far thats 3 out of 10 bad from the last set from utsource. I've put them to one side to test in more detail later.

Attached circuit, using a 10k multiturn preset and 470pF. With 0 ohm the delay from xout rising edge is 48ns and still shows spurious writes to F10.

Increasing resistance to increase the delay and the spurious writes to F10 stop at about 180 ohm. This gives a delay of 70ns from rise of Xout to rise of NENIN.

i also increased the delay further to the rising edge of the next xout cycle and beyond, but could not reintroduce the fault, so I think further investigation is needed.