Quote:
Originally Posted by Slothie
I was wondering if we could use the rising edge of NADS to gate NENIN, as every read/write operation is always preceded by NADS, the downsides to this is that it is an ugly kludge, and that executing DLY statements would probably break it, as I don't beleive the SC/MP processes any memory cycles during a DLY. Also the original board didn't need NADS, so we shouldnt need it. I get the feeling that our friends at SoC might have had to do some "fine tuning" of their circuit to get it to work. It seems to me it is using NENIN in a way it wasn't intended to be used, ignoring NENOUT and NBREQ. Although you shouldn't be able to break the system by just asserting NENIN at an inopportune moment.
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It seems the 8060 doesn’t respond to NENIN as quickly as it is implied in the datasheet, I’ll need to think again about how the multiprocessor can control bus access without the impact of delay from NENIN to NENOUT.
I was thinking we could detect a write cycle using NADS and RFLG, and hold off until NWDS rising edge, but not even sure if that would be early enough detection of a write cycle after seeing how late NWDS can start after NENIN is raised.
For the SoC vdu to work it must be down to timing of NENIN from XOUT, I don’t see any other inputs from the MK14 that could be used.