Re: Power MOSFETs
Andy, have you and your friend been able to confirm how much power is being dissipated by each device, and what variation you are getting in power dissipation between each device, and whether that aligns with case temperature (from a small thermocouple or IR) and the heatsink general temp, and the anticipated Rc-hs, and how that correlates back to Tj, and whether Tj is sufficiently derated below the rated max Tj=150C ?
That all also needs to be compared against expected DC power supply consumption, just in case you have another unexpected power loss going on (like hf oscillation that doesn't show up in an rms or dc meter reading at the device).
It looks like you are operating the FETs in the linear region. Is the source ballast resistance sufficient to force acceptable current sharing as device parameters change with temperature? Is your bias able to adjust with changing device temp? Is your gate stopper not too high in resistance so as to lose control of gate voltage due to transient or fast changing drain voltage (causing Cdg to influence Vgs)?
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