[pitbuell94]

Hi PPPPenguin and Darryl,

I have a question.

What happens in my last FIFO design when the wr-ptr and rd-ptr reach the last position?

I suppose the counter return to 0 or first writtable position, isn't-it? and the same for readpointer?

If this way of thinking is right, I don't need to add to my design a signal to reset WR-ptr and RD-ptr in this way => Read-reset and write-reset.

Then my fifo will run for ever till signal wr-clk and wr-en are on and I just need to take care about signal RD-data, wr-data, wr-clk, rd-clk, rd-en and wr-en.

Of course, I use rst signal to reset everything.

Thank you for your help.

Frédéric.