Quote:
Originally Posted by ppppenguin
There is an important app note from Xilinx that says very strongly: "Don't use global async reset". It may be useful for simulation but it's a very bad idea for synthesis.
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Are they referring to the GSR of the STARTUP Block here? This would be a bad thing to use in the case of a design with multiple asynchronous clocks since you would almost certainly have metastability coming out of reset.
For what ever reason, Xilinx and most of their IP partners love to use the async clr/pre. I just got some code from a third party IP partner of Xilinx's, and beside them doing things like forcing async delays to makeup for clock delays (always a bad thing) every single process starts with an async IF for the clr/pre's. I have done this in specific situations, but also prefer that everything stay synchronous.
Darryl