I tried to find the Franklin oscillator in June '78 Radcom TT but couldn't locate that particular magazine. However, google did find the original article for the VE3RF Franklin VFO on page 64 here:
https://www.americanradiohistory.com...dio-198911.pdf
There are some interesting comments in the text. VE3RF seemed to be struggling for loop gain and had to up the capacitance of the coupling caps to 10pF to get it to start reliably. This hints at a very low loop gain and this may be due to the Idss of the JFETs he used. Maybe the Vds of the FETs was very low in his circuit due to a higher standing current through the 1k resistors? He only got 1.2Vpkpk RF at the output of the second JFET and this seems very low.
The various JFET models I played with gave huge variations in loop gain and hinted that with a 2N5484 and 10p coupling caps the (excess) loop gain was huge and the coupling caps could be as low as about 1-1.5pF before the loop gain fell below unity. With a 2N5486 the loop gain fell below unity even with 10pF caps. I tried changing the coupling caps in my 'real' test oscillator in the shielded box and I could reduce the caps down to 1.2pF and it still oscillated reliably. This agreed with the simulation very closely.
His circuit also has some shunt capacitance at the input to his buffer because he has a 62pF and 150pF capacitive tap ahead of the buffer amp. This buffer amp looks a bit dodgy especially as it directly feeds a LPF at the emitter but the capacitive tap does introduce some phase shift into the loop via an RC network.
Without this external shunt capacitance a simulation of the loop response looks like the plot below. This shows that the zero degree phase point (marker 2) is not aligned with the peak in loaded Q at marker 1. This is not good for stability. This was the first odd thing I spotted about this oscillator design and I think this is caused by the 1k drain impedance at the first JFET on the left. The external buffer capacitance does shift the phase back to where it should be but this does seem to be an unconventional fudge method. Who knows, maybe it is the work of genius because it might help with temperature compensation in some way but introducing an RC defined phase slope in the feedback loop is a bit odd. But it is there!
If this circuit was modified to operate at a higher frequency I'd be a bit concerned about the capacitance of any external buffer amplifier. By 18MHz there might not need to be much capacitance here and having an external shunt capacitance of (say) 62pF will affect the loop gain and phase around the loop as it will introduce a significant RC filter into the loop that will introduce a lot of phase shift and slope.
Normally, the only place you want any phase slope (at the operating frequency) is in the resonator and you want this slope to be very steep (at the zero phase crossing point) if you want good phase noise and stability. If you look at the phase vs gain vs loaded Q plots of my MMIC oscillator in post#47 you can see that the zero phase crossing point is centred at the peak in gain and the peak in loaded Q. This is how it should be for good phase noise and stability.