[SiriusHardware]

That shows that all address lines are good at least as far as the output side of the address buffers. If you can now do the chip-select checks that Mark suggested?

For example, put scope probe (1) on pin 20 (CS1) of UD9 and scope probe (2) on DA0, ideally of the CPU socket. If you scope the data lines there you will be looking at them after they have passed through the databus buffers. I can appreciate that you might not be able to get to the 6502 socket data pins because of the NOP gizmo sitting on top, in which case you will have to scope the data lines on the left side of UE9 / UE10.

Whatever happens on the D0 data line while the PROM pin 20 is high is not really important, but during the period when pin 20 is low you should see line DA0 go to a distinct good logic 0 or logic 1 level - if you spread the sweep time out so you can see quite a few chip select pulses on scope channel 1 you should see that during some of the chip select pulses the D0 line is driven high and during other chip select pulses the D0 line is driven low. This is because on each successive chip select, a different address in the PROM is being read from. In some of the addresses bit 0 will be a logic '0', in other addresses bit 0 will be a logic '1'.

Repeat this for PROM CS1 vs. DA1 to DA7 of the databus, again looking to see good logic levels arriving at the CPU socket during chip select=low.

Then do this for the other three PROMs UD6-UD8.