Hi,
After ckecking, the sync line signal is good.
It seems to be that there is problem with the data stored in the FIFO.
In normal way, For each line I have 510 pixels. => 510 * 80 ns = 40.8 µs (visible video in 819 line standart) but I think I sample for example "X" sample in entrance ( 625 lines) and I have for example for output signal "X" + or - Delat value.
Because of this, the next line on the screen never start at dot "0" but at Dot "0" + Delta depending of the line number shows in the screen
.
I need to go back to sckool to calculate the start and the stop value of the sample function.
In parallel, I have a lot of problem with my hardware design.
Because there is some problem with the 5V, the less signifiants bits are not taken in account => bit 0, 1 and sometime 2...
I rebuild soon a new PCB with separate power supply voltage for each part( Digital, analog and final amplifier stage).
Fred C( Pitbuell94).