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pitbuell94 · 7th Apr 2011, 2:37 pm

Hi Tubesrule and PPPPenguin,

Can I disturb you concerning stranges things in VHDL?

All my single design work OK into my NEXYS2 board and by ISE simulator.

When I put all them into a single design, 3 of these files show warning > FIFO2, 819 and INTERPOLATOR.

Did you have any idea ?

Thank you very much for your support.

Frédéric Cabanes.

7th Apr 2011, 2:37 pm	#67
pitbuell94 Retired Dormant Member Join Date: May 2009 Location: Fresnes, France Posts: 124	Re: 819 line standards convertor. Hi Tubesrule and PPPPenguin, Can I disturb you concerning stranges things in VHDL? All my single design work OK into my NEXYS2 board and by ISE simulator. When I put all them into a single design, 3 of these files show warning > FIFO2, 819 and INTERPOLATOR. Did you have any idea ? Thank you very much for your support. Frédéric Cabanes.