Quote:
Originally Posted by merlinmaxwell
Almost, 7400 is a quad nand, A=1, B=1 so Q=0, use another of the four to invert the output.
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So, just checking...
for example with reference to the diagram - we're dropping the UCC37321 and 37322 and replacing them with gate drivers with no ENA pin.
We're doing this with a 7400.
...pins 1A and 1B of 1/8 of a 7400 output to pin 1Y. 1Y is input to pins 2A and 2B connected together. Their output, 2Y is the inverted output we need for the first gate driver.
This is repeated for the second gate driver, using the other two gates of the 7400, and this is how we have our 'virtual ENA' pin on the complimentary pair of gate drivers.
Segment of original circuit showing J-K flip-flop connection to the gate drivers that I'm not using.
(Not relevant to this post, but for context: CLR senses a one-shot pulse in overcurrent conditions. It resets the flip-flop on the next peak of the drive signal if the fault condition has cleared. If there is no fault condition the drive signal continues to be PWM modulated by an ‘interrupter.’ This merely pulses on and off at a variable low frequency to reduce the duty cycle of the power devices.