Quote:
Originally Posted by Slothie
According to this PDF by the highly regarded Steve Ciarcia the trick is to gate the chip enables OE and WE with the MREQ signal (pages 117, 126) |
The Ciarcia design is a good starting point for a simple z80 system, but it still doesn’t avoid chip enable to the 2114 before the write enable is active. The timing diagram he used shows memory request is earlier than write enable. The only mitigation I can see is that memory chips were smaller and slower so there would be delays in chip enable from the longer address control decode path and the ram would take longer to put data on the bus, though I don’t think the 2114 output buffers would be so slow to turn on that they would not try and drive against the data bus buffers.
He could have disabled the data bus buffers during write but he only uses the read enable to control direction.
I wonder how many people built his design and found interupt mode 2 would not work.